Should a termination resistor be implemented between DDR_CK pin and DDR_CKB pin?

[tanaka_shinsuke]

Dear Sirs or Madams,

Please let me know whether a resistor should be implemented between DDR_CK pin and DDR_CKB pin

as a termination when LPDDR is connected to K61.

And, if a termination resistor is needed, please let me know appropriate resistance.

  Note : I guess it is possible that the appropriate resistance depends on the layout design of the PCB.

             And if my guess is correct, please let me know it.

Best regards,

Shinsuke Tanaka

[miduo]

Hello,

Before to answer your question, I am not sure if you had aware of the errata for K61. See below:

So we do not have a recommend on "need" or "need not". The only suggestion is to try adjusting the series resistor values to delay the clock on your board to meet the spec.

[tanaka_shinsuke]

Dear Fang Li,

I appreciate your rapid response.

Please let me have two additional questions regarding your comments and high/low pulse width.

Q1.

Do you mean that we can adjust the ratio of High pulse width and Low pulse width

by adjusting the resistance implemented between DDR_CK pin and DDR_CKB pin?

For example, can we change the ratio of the clock signal

from "High width"/"Low width" = 45%/35% to 40%/40% by adjusting the resistance?

  Note : On the above example I set the sum of "High width" percentage and "Low width" percentage 

             to only 80%, NOT 100%. The reason is as follows;

               Regarding High width, I understand that the "transition time" of clock signal from Low to High

               can NOT be taken into consideration on the measurement of "High width".

               So, I think the total of  "High width" percentage and "Low width" percentage is always smaller than 100%

Please let me clarify your point, just in case.

Q2.

Are there any ways to increase both  "High width" percentage and "Low width" percentage

of clock signal simultaneously?

In other words, are there any ways to shorten both rise time and fall time

of the clock signal simultaneously?

  Note : I now understand that the adjustment of the resistance between DDR_CK pin and DDR_CKB pin 

             increases only one of "High width" percentage and "Low width" percentage

             and decreases the other one.

Best regards,

Shinsuke Tanaka

[miduo]

Hello,

Well, I am thinking that you may misunderstood the "clock crosspoint". If clock crosspoint is not located at 50% of signal amplitude, that sometime takes place since rising and failing slopes differ. Such effect may influence on operations of JEDEC.

[tanaka_shinsuke]

Dear Fang Li,

I appreciate your teaching.

>Well, I am thinking that you may misunderstood the "clock crosspoint".

Yes, I misunderstood about the clock crossing point.

Based on your explanation and also on the errata e9296, I now understand as follows;

(Here, I focus on LPDDR to simplify the discussion.)

1) The crossing point voltage of the clock signal outputted from these pins can be adjusted

    by implementing a resistor between DDR_CK pin and DDR_CKB pin.

2) The resistor implemented between DDR_CK pin and DDR_CKB pin is

     NOT directly related to High pulse width and Low pulse width of the clock.

 3) On the Rev.7 datasheet of K61P256M150SF3, Table 26 says that Vox-ac for LPDDR is 

     Min 0.4*VDD_DDR/ Max 0.4*VDD_DDR.

     But this includes typo and correct values are;

     Min 0.4*VDD_DDR/ Max 0.6*VDD_DDR.

4) The above-mentioned description regarding Vox-ac means that

    K61 controls the clock outputted from DDR_CK pin and DDR_CKB pin so that

    its crossing point voltage is within the range between 0.4*VDD_DDR and 0.6*VDD_DDR for LPDDR.

5) Roughly speaking, e9296 says the following two points;

      a)There is a possibility that crossing point voltage of the clock outputted from DDR_CK pin and DDR_CKB pin

        is out of the range between 0.4*VDD_DDR and 0.6*VDD_DDR for LPDDR,

        which violates the specifications on Vox-ac shown on the K61 datasheet.

        For example, it is possible that the crossing point voltage may become 0.65*VDD_DDR for LPDDR.

        (But this will be fixed at 5N96B mask set.)

      b)One possible countermeasure to the problem mentioned on above a)

         may be adjusting the crossing point voltage by adding a termination resistor,

         which means the resistor implemented between DDR_CK pin and DDR_CKB pin.

Are above 1)-5) correct?

I'm sorry to  bother you repeatedly, but if the above 1)-5) include any mistakes,

please let me know them.

Best regards,

Shinsuke Tanaka

[miduo]

Hello, Shinsuke Tanaka

Yes, all the above 5 points you mentioned are correct. Actually from our experience & observation, under most circumstance, even the clock crossing point out of spec, we do not see malfunction. Anyway, this had been fixed in new revision.

[tanaka_shinsuke]

Dear Fang Li,

I appreciate your rapid response.

And, I'm sorry for my repeated questions, but would you please let me have some additional questions

regarding this topic?

Q1.

Does a resistor implemented between DDR_CK pin and DDR_CKB pin have influences

ONLY on the crossing point voltage of the clock signal?

Or, does a resistor implemented between DDR_CK pin and DDR_CKB pin also affect the signal integrity?

(In other words, will the resistor decrease(or increase) the reflections on the DDR clock signal lines?)

Q2.

We found AN2582(Rev.6) document on NXP HP.

And, on the Table 3 on this document, there is the following description;

  "100–120 Ω is recommended as Differential termination of clock signals.

   (Required only for discrete implementations. DIMM modules provide the differential termination.)"

On the condition that discrete DDRs are connected to K61, 

does the above "Differential termination" mean

the resistance of a resistor implemented between DDR_CK pin and DDR_CKB pin?

In other words, if a resistor is NOT implemented between DDR_CK pin and DDR_CKB pin,

in such case the "Differential termination" should be considered as 0ohm?

Q3.

From the above AN2582(Rev.6)  Table 3 description,

it seems for me that

it is recommended a 100ohm-120ohm resistor should be implemented  between DDR_CK pin and DDR_CKB pin.

But on the other hand, according to your first response on this topic, you mentioned

"we do not have a recommend on "need" or "need not"."

So, currently it seems for me that the above description on AN2582(Rev.6) Table 3 and your comment

is not necessarily consistent with each other.

So, I'm wondering how I understand the necessity of the resistor.

I now understand as follows;

   The above description on AN2582(Rev.6) Table 3 is just a recommendation, NOT an obligation .

   And, whether the 100ohm-120ohm resistor is needed between DDR_CK pin and DDR_CKB pin

   depends on the design of the PCB on which K61 is used, e.g. layout of DDR clock signals or the types of DDR etc. 

Please let me know if my above understanding is correct, just in case.

Best regards,

Shinsuke Tanaka