Schematics to implement power sequencing of MK70FN1M0VMJ12

[puspamnayak]

Hi,

Greetings for the day !!!

I am using MK70FN1M0VMJ12 in my project so request you to provide schematics for reference to implement Power-Up and Power-Down sequence in my design.

As per page no. 27 of datasheet I need to follow the power sequencing in my design. I have referred  Tower board schematics but not getting the power section where this power sequencing is implemented

Kindly help me regarding this

Thanks and Regards,

Puspam Nayak

[chris_brown]

Hi Puspam,

The power sequencing on the tower board is guaranteed by sourcing the VDD, VDD_int, and VDDA power pins from the same electrical node (and therefore, the same source).  VDD_DDR is sourced from a power regulator downstream of the P3V3 source (which powers the other domains).  So we rely on the cascaded power supply to guarantee that VDD_DDR is powered after the other supplies.  Does this make sense?

Hope this helps,

Chris