SWreset - howto?

[OldNick]

The relevant chapter on the SCB is missing from the Kinetis RM, and I want to be able to call a SWreset to force a jump back to a bootloader from an application. (Sections defined in MKxxblah.h but no explanations)

Short of wiring an IO pin back to the reset input the SWreset bit looks like the best option.

Anybody done this?  Know how?  Found any gotchas?

[bressan]

try:
NVIC_SystemReset();
if you're lucky, your headerfiles do everything for you.

[robmeades]

Hi there.  I have a related question.  I use the above reset mechanism quite successfully on my LPC1768 but I now want to use it in an interrupt routine.  However, when I do that the LPC1768 stops dead: it does not reset. If I let the target run normally and then stop it in the debugger once my interrupt routine has triggered, it seems to be running a loop in the boot code up at 0x1FFF0BA2:

0x1FFF0BA2 : LDR r0,[r4,#0x14]
0x1FFF0BA4 : LSLS r0,r0,#28
0x1FFF0BA6 : BMI __StackTop+268340130 ; 0x1FFF0BA2

...where R0 is 0xF0000000 and R4 is 0x2009C000 but it never actually boots.

Any ideas what I'm doing wrong?

Rob

[mridulpandey]

I am using a KL26z microcontroller and  unable to write AIRCR register i tried this bunch of code can't change the value of SCB->AIRCR. Is there some way i could write to this register. I am using a BSP for FRDM-KL26Z on keil software.

vectkeyVal=0x5fa;
vectkeyVal=vectkeyVal<<16;
SCB->AIRCR &= 0x00001111;
SCB->AIRCR |= vectkeyVal;
SCB->AIRCR |= 4;

while(1);

above is the code i tried please help me out for this.

Thanks,

[BlackNight]

Hi Mridul,

can you use the code from https://mcuoneclipse.com/2015/07/01/how-to-reset-an-arm-cortex-m-with-software/ ?

(I have not tried that with Keil, but should work that way).

I hope this helps,

Erich

[mridulpandey]

Thanks for the reply Erich. Its working now.I learned that while writing the VECTKEY and the SYSRESETREQ there should be no instruction gap. It should be on the same instruction that worked for me. I just wrote.. 

SCB->AIRCR=0x05fA0002; 

this resulted in a reset :smileyhappy:

[hemant2007]

Hi to all,

I am using Cortex m4 processor from freescale K22,

In boot loader i download my firmware and after that I do following steps to soft restart

   // Disable - WatchDog and disbled IRQ.

  WDT_DISABLE();

  Disable_ALL_IRQ();

  DisableInterrupts;

  // Small delay is required before Soft RESET.

  delay1S();

  // SOFT RESET For K20  ???? is it right for k22 based mcu?????

    SCB_AIRCR = SCB_AIRCR_VECTKEY(0x05FA) | SCB_AIRCR_SYSRESETREQ(1) ;

while(1);

Now when MCU gets soft restart signal, next time it goes into CORE LOCK UP state

Ref:

ARM Information Center

ARM Information Center

Then it remains in Hard fault mode until i give power on reset then this hard fault state never occurs.

Can any body tell why this Hard fault state occurs when I soft restart?????? Also above code works well for k20 based MCU but then why not for K22 ?????

Thanks in advance!!!

[MikeyB]

There is a trick to it.  You have to write the key at the same time as the reset request.

     /* request software reset */     

      SCB_AIRCR = SCB_AIRCR_VECTKEY(0x5FA)| SCB_AIRCR_SYSRESETREQ_MASK;

      /* wait for reset to occur */

      while(1); 

[robertofrechill]

I like this so much!!!! :smileyhappy:

Thanks dude!

[emh203]

Did you look into this:

6.2.2.6 Software reset (SW)
The SYSRESETREQ bit in the NVIC application interrupt and reset control register can
be set to force a software reset on the device. Setting SYSRESETREQ generates a
software reset request. This reset forces a system reset of all major components except for
the debug module. A software reset causes SRSH[SW] bit to set.

from the kinetis reference manual?

You can also write "junk" to the watchdog to force a reset.

[OldNick]

emh203

Thanks.

My copy of the K_blah_RM.pdf has this

6.2.2.6 Software reset (SW)
The SYSRESETREQ bit in the NVIC application interrupt and reset control register can
be set to force a software reset on the device. (See ARM's NVIC documentation for the
full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module. A software reset causes
SRSH[SW] bit to set.

But what did they mean by "VECTKEY field requirments"?

Found nothing else on the subject.  Hence the question.

I gather from the Segger JLink tech docs that it uses SWreset to reset the Kinetis, but then has to turn the WDOG off immediately because kinetis defaults to WDOG enabled and the Jlink connection breaks if nobody is feeding the dog. (i.e. in a debug session).

Don't know if Freescale are intending to fix that.

thanks again

[admin]

Nick,

The SCB is the System Control Block. It's a Core part of the Cortex M3/M4 implementation so the best documentation is on the ARM InfoCenter website which you can find here.  That being said, the AIRCR.SYSRESETREQ bit is probably what you are looking for. 

Keep in mind that the reset generated by the SYSRESETREQ is asynchronous, so you'll need a while(1) after you alter it, much like as in a watchdog triggered reset.

Tom

[OldNick]

tkey,

Good link

Had been searching the ARM website for that, but not found it.

Relevant page says

4.3.5. Application Interrupt and Reset Control Register

The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in Table 4.12 and Table 4.17 for its attributes.

To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write.

The bit assignments are:

Table 4.17. AIRCR bit assignments

Bits Name Type Function

[31:16]	Write: VECTKEYSTAT Read: VECTKEY	RW	Register key: Reads as 0xFA05 On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
[15]	ENDIANNESS	RO	Data endianness bit is implementation defined: 0 = Little-endian 1 = Big-endian.
[14:11]	-	-	Reserved.
[10:8]	PRIGROUP	R/W	Interrupt priority grouping field is implementation defined. This field determines the split of group priority from subpriority, see Binary point.
[7:3]	-	-	Reserved.
[2]	SYSRESETREQ	WO	System reset request bit is implementation defined: 0 = no system reset request 1 = asserts a signal to the outer system that requests a reset. This is intended to force a large system reset of all major components except for debug. This bit reads as 0. See you vendor documentation for more information about the use of this signal in your implementation.
[1]	VECTCLRACTIVE	WO	Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
[0]	VECTRESET	WO	Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.

Love the bit about "see your vendor documentation!"