Yes, thanks. Changed Sources 16-17 for SPI0 to Sources 20-21 for SPI2. Mantain using channel 2.
Still not seeying pulse when transmitting data.
This is the code:
/********************************************************************/
void vfnMem_Set4TXDMA(unsigned long * u32ptrAddress) //PAGE PROGRAM
{
unsigned char i;
*u32ptrAddress++ = SPI_PUSHR_CONT_MASK | SPI_PUSHR_PCS(0x1) | 0x0200; //opcode 02 and 1 byte of address
*u32ptrAddress++ = SPI_PUSHR_CONT_MASK | SPI_PUSHR_PCS(0x1) | 0x0000; //other 2 bytes of address
for(i=0;i<126;i++)
{
*u32ptrAddress++ = SPI_PUSHR_CONT_MASK | SPI_PUSHR_PCS(0x1) + i; // data to be written
}
*(--u32ptrAddress) |= SPI_PUSHR_EOQ_MASK;
*u32ptrAddress &= ~SPI_PUSHR_CONT_MASK;
}
/********************************************************************/
void vfnDMA_Init_Tx(void)
{
// use dma to program the chip
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
DMA_ERQ = DMA_ERQ_ERQ2_MASK; //channel 2
DMAMUX_CHCFG2 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(21) ; //Source 21 for SPI2 transmit
/* Set the Source Address */
DMA_TCD2_SADDR = (_SOFT_U32BITS)(CORE_SRAM_ADDR + 0x10 );
/* Destination address */
DMA_TCD2_DADDR = (_SOFT_U32BITS)&SPI2_PUSHR;
/* Source offset disabled */
DMA_TCD2_SOFF = 0x04;
/* Source and Destination Modulo off, source and destination size 2 = 32 bits */
DMA_TCD2_ATTR = DMA_ATTR_SSIZE(2) | DMA_ATTR_DSIZE(2);
/* Transfer 4 bytes per transaction */
DMA_TCD2_NBYTES_MLNO = 0x04;
/* No adjust needed */
DMA_TCD2_SLAST = 0x00;
/* Destination offset disabled */
DMA_TCD2_DOFF = 0x00;
/* No link channel to channel, 1 transaction */
DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(128);
/* No adjustment to destination address */
DMA_TCD2_DLASTSGA = 0x00;
DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(128);
DMA_TCD2_CSR = DMA_CSR_DREQ_MASK; //One transfer only.
}
/********************************************************************/
void vfnSPI_DMA(spi_ctl *spi_value)
{
SPI2_MCR = SPI_MCR_MSTR_MASK | SPI_MCR_CLR_TXF_MASK |SPI_MCR_CLR_RXF_MASK | SPI_MCR_PCSIS(0x1) | SPI_MCR_HALT_MASK;
SPI2_CTAR0 = SPI_CTAR_FMSZ(0xF) | spi_value->br | spi_value->cpha | spi_value->cpol;
SPI2_RSER = SPI_RSER_TFFF_RE_MASK|SPI_RSER_TFFF_DIRS_MASK;
SPI2_MCR = SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS(0x1) | SPI_MCR_HALT_MASK;
/*Start transmition*/
SPI2_MCR &= ~SPI_MCR_HALT_MASK;
while( !(SPI2_SR & SPI_SR_EOQF_MASK))
{}
SPI2_SR |= SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK ;
SPI2_MCR |= SPI_MCR_HALT_MASK;
}
And this is the command order:
vfnMem_Set4TXDMA(u32ptrBufAddress);
vfnMem_WriteEnable(&spi);
vfnDMA_Init_Tx();
vfnSPI_DMA(&spi);
When the last command (vfnSPI_DMA) isn't enabled, I see the WriteEnable command pulse (06h - 00000110) with the osciloscope.
But when all commands are enabled, the osciloscope doesn't get nothing.