SIM_SCGC6 is not declared

[neilporven]

Hi everyone,

I have the following issue, in my init.c I am using the following:

SIM_SCGC6 |= SIM_SCGC6_PIT_MASK | SIM_SCGC6_DMAMUX_MASK;

in my init.h I am including the following:

#include "MK64F12.h"

I brought both the init.c and .h from a Kinetis project that is working correctly to MCUXpresso.

I don't understand why this is happening?

 Under the project properties, I believe this is correct (I attached it):

[neilporven · Accepted solution]

Update,

My colleague figured it out.  

This was how you access the SCGC6 previously:

SIM_SCGC6 |= SIM_SCGC6_PIT_MASK | SIM_SCGC6_DMAMUX_MASK;

This is the way how to access it now!

SIM->SCGC6 |= SIM_SCGC6_PIT_MASK | SIM_SCGC6_DMAMUX_MASK;

[neilporven]

Ok, so I opened both Kinetis and MCUXpresso and compared MK64F12.h files and I noticed the following:

This is for Kinetis:

Processors: MK64FN1M0VDC12
** MK64FN1M0VLL12
** MK64FN1M0VLQ12
** MK64FN1M0VMD12
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.8, 2015-02-19
** Build: b150225

and this is for MCUXpresso:

Processors: MK64FN1M0CAJ12
** MK64FN1M0VDC12
** MK64FN1M0VLL12
** MK64FN1M0VLQ12
** MK64FN1M0VMD12
** MK64FX512VDC12
** MK64FX512VLL12
** MK64FX512VLQ12
** MK64FX512VMD12
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.9, 2016-03-21
** Build: b180801

In Kinetis they forgot to mention the 512 processors (just an observation).

In MCUXpresso they included the 512s.

The other observation was the Build, it seems that changes were done on MCUXpresso and possibly the following

was removed:

/* SIM - Register instance definitions */
/* SIM */
#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
#define SIM_SDID SIM_SDID_REG(SIM)
#define SIM_SCGC1 SIM_SCGC1_REG(SIM)
#define SIM_SCGC2 SIM_SCGC2_REG(SIM)
#define SIM_SCGC3 SIM_SCGC3_REG(SIM)
#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
#define SIM_UIDH SIM_UIDH_REG(SIM)
#define SIM_UIDMH SIM_UIDMH_REG(SIM)
#define SIM_UIDML SIM_UIDML_REG(SIM)
#define SIM_UIDL SIM_UIDL_REG(SIM)

where SIM_SCGC6 can be found.

Can someone from NXP explain this?

Thanks,

Neil