Hi, Victor,
Are you sure that the watchdog leads to the interrupt or reset event? after the code enters interrupt or reset, I suggest you check IPSR register in debugger, the Low 9 bits reflect the interrupt vector number, in this way, you can know the interrupt source. If it is Reset, you can check the RCM_SRSx so that you can know which leads to the Reset event.
If it is watchdog exactly which leads to reset/interrupt, you can put the the following disabling watchdog code ahead of all code. As you know that the the watchdog initial value after Reset is 0x4C0000, it is enough to reach up to the code to change setting up the watchdog generally.
Hope it can give you a clue.
BR
XiangJun Rong
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = (uint16_t)0x01D2u;
#endif /* (DISABLE_WDOG) */