SAI interface in both direction simultaneously. (MQX 4.1 / K70)

[poul-erikhansen]

I am using a K70F512 and uses the MQX RTOS version 4.1.

I need to use the SAI interface in both directions simultaneously, and I need to know the exact delay from D/A-converter to A/D-converter because I need to measure audio phase difference down to 1 degree at 10KHz.

Do you have a example of initialize both direction in one call ?

How can I make sure that I don't get one audio clock sample difference in the timing from time to time ?

Poul-Erik.

[xiangjun_rong]

Hi, Poul Erik,

We have example code for I2S module of  K70 based on MQX os, I suppose you have installed MQX, pls refer to the directory:

C:\Freescale\Freescale_MQX_4_0\mqx\examples\i2s_demo, there is example called "i2s_demo_twrk70f120m", I think you can run the code. No matter whether the frame clock/bit clock are from K70, ADC or DAC, I think you can use synchronous mode(both receiver/transmitter use the same bit clock and frame clock), even you can use asynchronous mode, but the same bit clock/ frame clock signals drive both the transmitter and receiver, in the above case, the DAC and ADC converters receve/transmit data at the same time, in other words, they sample simultaneously. I do not know what the  "phase difference" means and how you measure it.

I suppose you get the ADC sample firstly, in the next I2S cycle, you output the ADC sample to DAC, then test the phase difference, in theory, they has one conversion time phase shift, the additional phase shift is the difference of ADC and DAC conversion time.

If you use MQX os, I suspect that the receiver/transmitter data are saved in respective buffer, if you want to test the phase shift, I think it is okay to  just use interrupt mode without MQX.

[poul-erikhansen]

I have tried the i2s_demo but:

     1) The one supplied with MQX 4.1 is one direction (Play or Record).

     2) There are no support for TWR-K70F12 only for TWR-K60. I have tried to port the K60 setup but I never got it working.

Regarding phase difference: It is the time delay between to signal relative to the time period. This mean that a 1us difference on a 10kHz signal will give a phase difference of 3.6 degrees.

Poul-Erik.

[egoodii]

When dealing with sampled systems, and in particular sigma-delta ADC/DAC, the time-shift is called 'group delay' and will consist of the ADC group delay (the more filtering, the longer...), queue delay, K70 processing to outbound queue, thence DAC filtering delay. For a full multi-channel DMA-driven double-buffered data streaming example, I can only suggest my I2S/DMA example in community.freescale.com/message/82190#82190.  It was written for version 1 silicon (SSI), so if you have the 'version 2' SAI block in your chip, I'm afraid there will be differences, but the general concepts remain, especially how to use the DMA 'half interrupts' to do all the double-buffer work, and the minor/major loop-count-factors to interleave/de-interleave isolated linear buffers.  Buffer size will be part of your overall 'group delay' (sample times) as you process one 'buffer full' from 'in' to 'out'.

[poul-erikhansen]

Thank you for the answer. I know that I have to compensate for the ADC and DAC delays, but it must be equal all the time, or i need to loop back the analog signal after initialization and the measure the difference and compensate.

Poul-Erik.

[egoodii]

Certainly the SAI bus & queuing delays will be 'constant', and as long as your K70 computations in processing an 'in' buffer to an 'out' buffer are ALWAYS completed in less than 'one queue full' of time, that delay will also be a constant, based on sample rate & count(queue size).  So your overall group-delay from 'analog in' to 'analog out' will be very consistent and easily specified.  If you buffer 2ms worth, for instance (64 samples at 32KHz) each sample that comes 'in' will pop back 'out' 4ms later (appropriately modified, of course) or 128 sample-delay.  Add a couple for the SSI bus delay, and then a 'nice cheap CoDec' like TI 320AIC3104, which specs a 17 sample ADC group delay, and 21 sample DAC group delay, and you have your total group delay.