S9KEAZN64AMLC Failure of double-edge sampling measurement period

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S9KEAZN64AMLC Failure of double-edge sampling measurement period

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Contributor III

Double Edge sampling using FTM2(CH2&CH3) of S9KEAZN64AMLC , sample the period of  pwm signal .

When the duty cycle is greater than 95%,The measurements are incorrect.("20KHz" has been misidentified as "10KHz ").

Can the IC measure the period of a signal with a duty cycle greater than 95% ? If it can be collected, what should we pay attention to when designing?

pastedImage_1.png

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang ,

   Thanks for your interest in the NXP kinetis product, I would like to provide service for you.

   Do you want to detect both the PWM duty and the frequency, right?

   What's the FTM clock you are using? Bus clock 20Mhz? Core clock is 40Mhz, right?

   Do you try to just use signal edge to detect the 20Khz frequency PWM?

   Does it work?

   Or just when you use the Double Edge sampling which also want to get the pulse, 95% duty cycle, it meas the double edge interrupt should detect the 5%*20K= 2.5us.

   Please note, the FTM double edge sample,two edges detect is also using the same FTM2 interrupt ISR.

  From this link:

   Beginner guide on interrupt latency and Arm Cortex-M processors - Processors blog - Processors - Arm... 

You can get that:

 pastedImage_2.png

  That means, the interrupt latency+ your ISR interrupt service code time should smaller than the 5%*20K= 2.5us.

  So, if your core clock is 40Mhz, then you can check your ISR serive code, whether all the execute time is larger than 2.5us when you can't detect the correct frequency?

   Because if your ISR execution time is very long, when the next edge interrupt happens, you will lost the interrupt, it will have problems. So in your ISR, code should be as small as possible, save the execute time.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Kerry

 

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NXP TechSupport
NXP TechSupport

Hello zhiyong zhang,

  Sorry for my later reply!

  Today, I do more testing, now it can capture upto 99%(990/999=99%).Even 40Khz.

pastedImage_1.png

Please check my test result:

pastedImage_3.png

pastedImage_4.png

Modify points:

1. I set the  FTM clock to 40Mhz,  ICSOUTCLK div by1

SIM_CLKDIV = 0x01000000;

2, I modify your FTM2 ISR

void FTM2_IRQHandler(void)
{
/*
FTM_ClrChannelFlag(pFTM2, FTM_CHANNELPAIR2);
FTM_ClrChannelFlag(pFTM2, FTM_CHANNELPAIR2+1);
*/
if(FTM2_C5SC & FTM_CnSC_CHF_MASK)
FTM2_C5SC &= ~(FTM_CnSC_CHF_MASK);
/* if(FTM2_C4SC & FTM_CnSC_CHF_MASK)
FTM2_C4SC &= ~(FTM_CnSC_CHF_MASK);*/

captureFlag = 1;
/*
if(FTM_Callback[2])
{
FTM_Callback[2]();
}
*/
}

Then in main

while(1)
{
if(captureFlag == 1)
{
captureFlag = 0;
OUTPUT_TOGGLE(PTF, PTF7);
}


}

Please check my attached project, it is modified based on your project.

Kerry

 

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang,

 Thanks a lot for your patient!

  Today, I have tested your board on my TRK-KEA128, because the FRDM-KEA128 isn't available now, TRK is the same.

  I have totally reproduced your issues, when FTM2 capture the 20Khz, duty larger than 96%, the issue will be reproduced.

  I have removed your FTM1 PWM wave, and use the waveform generator generate the PWM, the same situation, I even call the GPIO toggle in the FTM ISR directly without the callback, the same issue.

  So, I need more time to test it, and check with our internal side, maybe really like you said, have the smallest puse capture limit. I checked the code, it didn't add the capture filter.

   Anyway, please give me more time, any updated information on my side, will let you know.

   Thanks a lot for your understanding.

Best Regards,

Kerry

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang,

   Just double check with you the test situation, you are using S9KEAZN64AMLC, right?

   But, I find your project is using SKEAZ64.

  Please also tell me, which external OSC you are using? 8Mhz?

  Please note, KEAZ64 and KEAZN64 have the difference, KEAZ64 FLL factor is 1280, but KEAZN64 FLL factor is 1024.

  I find your code is using KEAZ64, but in your previous post, you tell me you are using KEAZN64, please double check your situation. You can also share your schematic about the smallest system.

   BTW,do you use FTM1 output the PWM, then use FTM2 to capture it? And the FTM1 modify the duty cycle?

   Please also tell me your test situation, which detail pin you are using now, then I can do more research and testing.

   My side KEAZN64 just have the TWR-KEA64, and this board don't have the external crystal, maybe I need to use the internal IRC as the clock source.

Waiting for your reply!

Kerry

 

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Contributor III

Hi,Kerry

The product uses the S9KEAZN64ALMC,but current test use the S9KEAZ128AMLK in the
FRDM-KEAZ128Q80,use the external OSC. 

Yes,we use FTM1 output the PWM, then use FTM2 to capture it. And the FTM1 modify the duty cycle.

The FTM2 used PTG6&PTG5,the FTM1 used PTE7.

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang

  That's good to hear you are using the FRDM-KEAZ128Q80, then I can test it directly.

   Today, I am working at home, and no board on my side, tomorrow, I will back to the office and help you to test it.

   Any updated information, will let you know, please keep patient, thanks.

Best Regards,

Kerry

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23 Views
NXP TechSupport
NXP TechSupport

Hi zhiyong zhang ,

   Thanks for your interest in the NXP kinetis product, I would like to provide service for you.

   Do you want to detect both the PWM duty and the frequency, right?

   What's the FTM clock you are using? Bus clock 20Mhz? Core clock is 40Mhz, right?

   Do you try to just use signal edge to detect the 20Khz frequency PWM?

   Does it work?

   Or just when you use the Double Edge sampling which also want to get the pulse, 95% duty cycle, it meas the double edge interrupt should detect the 5%*20K= 2.5us.

   Please note, the FTM double edge sample,two edges detect is also using the same FTM2 interrupt ISR.

  From this link:

   Beginner guide on interrupt latency and Arm Cortex-M processors - Processors blog - Processors - Arm... 

You can get that:

 pastedImage_2.png

  That means, the interrupt latency+ your ISR interrupt service code time should smaller than the 5%*20K= 2.5us.

  So, if your core clock is 40Mhz, then you can check your ISR serive code, whether all the execute time is larger than 2.5us when you can't detect the correct frequency?

   Because if your ISR execution time is very long, when the next edge interrupt happens, you will lost the interrupt, it will have problems. So in your ISR, code should be as small as possible, save the execute time.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Kerry

 

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- We are following threads for 7 weeks after the last post, later replies are ignored
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Contributor III

Thank you for your help.

Yes,I want to detect both the PWM duty and the frequency, but Bus clock 16Mhz, Core clock is 32Mhz.

The PWM duty and frequency is changed.When the duty is less than 95%,the test results were correct.

When the duty is greater than 95%,the test results were incorrect.

If our ISR execution time is very long, when the next edge interrupt happens, lost the interrupt. 

If I could change the clock(Bus clock 20MHz,Core clock is 40MHz,or faster),Whether or not this problem can be solved?

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang,

   core clock 40Mhz is the max clock to your KEA chip.

   About whether it is enough, still like what I have told you, you need to measure your ISR exection time, whether it is smaller than your 5% duty. I think you can use the systick to test your ISR related execution time, please note, you also need to add the Cortex M0+ interrupt latency 15 core cycle time.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Kerry

 

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Contributor III

Hi  Kerry,

Thank you for your help.

We configure the Bus clock 20MHz,Core clock is 40MHz. Using the S32 Design Studio for ARM Version 2018.R1 development environment. Run the  code of appendices.

The current configuration:Using the FTM2_CH4(detect rising edge,disable interrupt)、FTM2_CH5(detect falling edge,enable interrupt).FTM1 output PWM(20KHz),Put I/O toggle in input capture interrupt.

1.When the PWM duty is 95%,can be captured normally,and into interrupt(execute IO toggle);

2.When the PWM duty is 96%,an interrupt will be lost.

Question:Why lose an interrupt? We only enable the interrupt of FTM2_CH5(detect falling edge). The time interval is 50μs of ever falling edge.

pastedImage_4.png

pastedImage_5.png

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang,

  I checked your code, I find your ISR code is really containing too many code.


void FTM2_IRQHandler(void)
{
if(FTM_Callback[2])
{
FTM_Callback[2]();
}
}

void FTM2_Task(void)
{

    static uint8_t flag = 0;
    static uint16_t old_Ch0Value, new_Ch0Value;

    OUTPUT_TOGGLE(PTF, PTF7);

    FTM_ClrChannelFlag(pFTM2, FTM_CHANNELPAIR2);
    FTM_ClrChannelFlag(pFTM2, FTM_CHANNELPAIR2+1);

 FTM_MemMapPtr pFTM = (FTM_MemMapPtr)FTM2;


 u16Ch0Value = pFTM->CONTROLS[4].CnV;
 u16Ch1Value = pFTM->CONTROLS[5].CnV;
 counts= (u16Ch1Value - u16Ch0Value);



    flag++;
    if (flag == 1)
    {
        old_Ch0Value = u16Ch0Value;
    }
    else if (flag == 2)
    {
        new_Ch0Value = u16Ch0Value;
        period = (new_Ch0Value - old_Ch0Value);             /* 20M */
//        printf("\n The input wave period is %i us\n", period);
        flag = 0;
    }


// period=(((.000000167)*(counts))*(1000000))*(2);   /* Operation to get the period of the output */
// printf("\n Dual edge capture end. The input counts are %d\n",(counts));
// printf("\n The input wave period is %i ms\n",period);
// pFTM->COMBINE |=  FTM_COMBINE_DECAP2_MASK |FTM_COMBINE_DECAPEN2_MASK;
}
/********************************************************************/
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

I suggest you move some code outside the ISR.

eg, in the ISR, just store u16Ch0Value, u16Ch1Value, clear the flag.

Then define one flag, which used to indicate the FTM2 interrupt is entered.

Then in your main code, when detect the FTM2 ISR entered flag is set, do the GPIO toggle, and other calculation code.

If it is still not enough, you can delete your callback, do the FTM channel clear and the value store in the void FTM2_IRQHandler(void) directly.

Please try it again.

If you still have questions about it, please kindly let me know.

Kerry

 

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Contributor III

Hi,Kerry

We only enable the interrupt of FTM2_CH5(detect falling edge),the time interval is 50μs of ever falling edge. So the interval between interrupt is also 50μs.

Why can the capture period be normal when duty cycle is 95%?But it failed when the duty is 96%?

And 50us interval, I should be able to perform these simple operations in the interrupt program.

Can you provide a reference program? Can capture period of PWM signal(duty greater than 95%).

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NXP TechSupport
NXP TechSupport

Hi zhiyong zhang,

  I will find time to help you to test it on my side.

  Please keep patient, I will test it on my TRK-KEA64 board, the on board chip is SKEAZN64MLH2.

  After I test it, I will let you know the result.

  Thanks a lot for your understanding.

If you still have questions about it, please kindly let me know.

Kerry

 

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