Double Edge sampling using FTM2（CH2&CH3） of S9KEAZN64AMLC , sample the period of pwm signal .
When the duty cycle is greater than 95%，The measurements are incorrect.（"20KHz" has been misidentified as "10KHz "）.
Can the IC measure the period of a signal with a duty cycle greater than 95% ? If it can be collected, what should we pay attention to when designing？
Hi zhiyong zhang ,
Thanks for your interest in the NXP kinetis product, I would like to provide service for you.
Do you want to detect both the PWM duty and the frequency, right?
What's the FTM clock you are using? Bus clock 20Mhz? Core clock is 40Mhz, right?
Do you try to just use signal edge to detect the 20Khz frequency PWM?
Does it work?
Or just when you use the Double Edge sampling which also want to get the pulse, 95% duty cycle, it meas the double edge interrupt should detect the 5%*20K= 2.5us.
Please note, the FTM double edge sample,two edges detect is also using the same FTM2 interrupt ISR.
From this link:
You can get that:
That means, the interrupt latency+ your ISR interrupt service code time should smaller than the 5%*20K= 2.5us.
So, if your core clock is 40Mhz, then you can check your ISR serive code, whether all the execute time is larger than 2.5us when you can't detect the correct frequency?
Because if your ISR execution time is very long, when the next edge interrupt happens, you will lost the interrupt, it will have problems. So in your ISR, code should be as small as possible, save the execute time.
Wish it helps you!
If you still have questions about it, please kindly let me know.
Kerry
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Hello zhiyong zhang,
Sorry for my later reply!
Today, I do more testing, now it can capture upto 99%(990/999=99%).Even 40Khz.
Please check my test result:
Modify points:
1. I set the FTM clock to 40Mhz, ICSOUTCLK div by1
SIM_CLKDIV = 0x01000000;
2, I modify your FTM2 ISR
void FTM2_IRQHandler(void)
{
/*
FTM_ClrChannelFlag(pFTM2, FTM_CHANNELPAIR2);
FTM_ClrChannelFlag(pFTM2, FTM_CHANNELPAIR2+1);
*/
if(FTM2_C5SC & FTM_CnSC_CHF_MASK)
FTM2_C5SC &= ~(FTM_CnSC_CHF_MASK);
/* if(FTM2_C4SC & FTM_CnSC_CHF_MASK)
FTM2_C4SC &= ~(FTM_CnSC_CHF_MASK);*/
captureFlag = 1;
/*
if(FTM_Callback[2])
{
FTM_Callback[2]();
}
*/
}
Then in main
while(1)
{
if(captureFlag == 1)
{
captureFlag = 0;
OUTPUT_TOGGLE(PTF, PTF7);
}
}
Please check my attached project, it is modified based on your project.
Kerry
-------------------------------------------------------------------------------
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- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------
Hi zhiyong zhang ,
Thanks for your interest in the NXP kinetis product, I would like to provide service for you.
Do you want to detect both the PWM duty and the frequency, right?
What's the FTM clock you are using? Bus clock 20Mhz? Core clock is 40Mhz, right?
Do you try to just use signal edge to detect the 20Khz frequency PWM?
Does it work?
Or just when you use the Double Edge sampling which also want to get the pulse, 95% duty cycle, it meas the double edge interrupt should detect the 5%*20K= 2.5us.
Please note, the FTM double edge sample,two edges detect is also using the same FTM2 interrupt ISR.
From this link:
You can get that:
That means, the interrupt latency+ your ISR interrupt service code time should smaller than the 5%*20K= 2.5us.
So, if your core clock is 40Mhz, then you can check your ISR serive code, whether all the execute time is larger than 2.5us when you can't detect the correct frequency?
Because if your ISR execution time is very long, when the next edge interrupt happens, you will lost the interrupt, it will have problems. So in your ISR, code should be as small as possible, save the execute time.
Wish it helps you!
If you still have questions about it, please kindly let me know.
Kerry
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------
Hi Kerry，
Thank you for your help.
We configure the Bus clock 20MHz，Core clock is 40MHz. Using the S32 Design Studio for ARM Version 2018.R1 development environment. Run the code of appendices.
The current configuration：Using the FTM2_CH4(detect rising edge，disable interrupt)、FTM2_CH5（detect falling edge，enable interrupt）.FTM1 output PWM（20KHz），Put I/O toggle in input capture interrupt.
1.When the PWM duty is 95%，can be captured normally，and into interrupt（execute IO toggle）；
2.When the PWM duty is 96%，an interrupt will be lost.
Question：Why lose an interrupt? We only enable the interrupt of FTM2_CH5(detect falling edge). The time interval is 50μs of ever falling edge.
