Restriction of Fractional Delay Circuit in KV5x to work

[seapon]

Document KV5X sub-family reference manual describes 

   a) "The fractional delay logic can only be used when the IPBus clock is running at 100 MHz."

       in  FRAC_PU bit description of PWMx_SMnFRCTRL field.

   b) "Using the micro-edge placer block requires that the Fast-Peripheral clock be set within a
      valid frequency range (see the data sheet of this device for minimum and maximum
      values) and the core/system clock must be programmed to be 2x the Fast Peripheral
       clock." in 48.5.2.9.1 Fractional Delay Logic with Nano-Edge Placement Block

  For above b), data sheet indicates 120MHz as max value of Fast-Peripheral clock.

  If Fast-Peripheral clock is set to  120MHz, fractional delay logic will not work by reason a) ?

 Please help how I understand this conflict of restriction.

 BR.

    Masato Nishimoto

[Alexis_A]

Dear seapon@seapons.com‌,

Check the following description for IPBus:

The Fast Peripheral Clock is part of the clock distribution and set in the MCG:

So if you'll need to set both clock to the respective ranges.

I hope this helps you.

Best Regards,

Alexis Andalon

[seapon]

Dear Alexis,

Than you for your mail.

To use the micro-edge placer block, we use MCGOUTCLK (=240MHz) and fast peripheral clock (=120MHz).

 However, FRAC_PU bit description of PWMx_SMnFRCTRL field mentions "The fractional delay logic can only be used when
the IPBus clock is running at 100 MHz.".

What is relation between Fractional delay logic and IPBus clock?

Where is IPBus clock comes from (I cannot find  IPBus clock at clocking diagram)?

How I can control frequency of IPBus clock?

Please let me know above.

Best Regards,

Masato Nishimoto

[Alexis_A]

Dear seapon@seapons.com‌,

Sorry but I made a mistake about this, the only clock that supply the PWM is the Fast Peripheral Clock.

So you'll need to set the core clock at 200 MHz if you want  fractional delay logic.

I'm sorry for this mistake.

Best Regards,
Alexis Andalon