RM or SDK for the K20 Is it wrong?

[pietrodicastri]

Good morning

I refer to K20P100M72SF1RM.pdf. 

There are two others K20 RM all of them have the same inconsistency it seems to me

The  section

5.7.4 PORT digital filter clocking 

is referring to the clock for the digital filter input. 

The register PORTx_DFCR[CS] is referred.

The problem is no one of the K20 RM mention the DFCR register. It seems the DFCR and the DRWR are not in use in this processor.

I define in the project the macro CPU_MK20DX256VLK10.

This will include the files 

MK20D10.h

and 

MK20D10_features.h

This last has the macro 

FSL_FEATURE_PORT_HAS_DIGITAL_FILTER 

enabling the DFER, DFCR and DFWR

Something is not in order in the SDK. Please have a look.

Thank You

Pietro

[kerryzhou]

Hi Pietro di Castri,

   Please help to confirm your chip part number at first: MK20DX256VLK10

 If yes, you need to refer to K20P81M100SF2V2RM.pdf

   

just these register:

So, please make sure your code matches your chip.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Kerry

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