Program and debug problems with KL15

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Program and debug problems with KL15

548 次查看
michaeltreumann
Contributor I

Hi all,

I have a board designed with a KL15Z128. My problem is that I can program the controller only sporadically and debug. I have find out that when the programmierrung failed, the reset line toggeld. If programming was successful, the reset line is high.

I also have a crosstalk of the clock line to the reset line

If a program is in the controller I have no problems to debug.

I use the J-Link debugger.

Here's what I've already tried:

Reset line pulled up.

SWDIOLeitung pulled up.

Capacitor between Reset and GND.

Unfortunately, all without success.

Does anyone have any idea what this problem is?

0 项奖励
回复
1 回复

421 次查看
Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Michael Treumann:

Can you share your board schematics or at least the part of the SWD connections?

The reset pin toggling is the normal behavior for a blank device.

Also, you see "crosstalk" between the clock line and reset lines. Check that there is not any kind of short circuit between these pins.

Some things you can check and design tips that have helped other customers to have a more stable SWD connection:

- Check that the MCU is well soldered (no loose pins or defective solder joints).

- Try placing a series resistor in the SWD-CLK pin.

- A pull-up resistor is recommended in the SWD_DIO line.

- In the Reset line, connect a pull-up resistor to VDD and a capacitor to GND.

- Check that the NMI pin (PTA4 in your case) is not pulled low by any external signal.

Let us know if any improvement.


Regards!,
Jorge Gonzalez

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 项奖励
回复