Problems getting the K10 EEPROM flex ram working

[julianmorrison]

Hello,
I am having no luck in getting the K10 EEPROM flex ram working.
The device is marked as M10AFV IN86B bought from Farnell and has been confirmed as a K10DX64 part.
I want to use all of Flex NVM for 2k of EEPROM.
No matter how I setup the the EEE_SIZE and DFLASH_SIZE the SIM_FCFG1 register always reports:
NVMSIZE = 3 (32k)
PFSIZE = 5 (64k)
EESIZE = 3 (2k)
DEPART = 0x0B (32k) - ie no EEPROM)
My code hangs waiting for EEERDY in FTFL_FCNFG

I am running Codewarrior 10.4 using a barebones project on the target K10 board and also tried this code on the K20DX part on the tower development kit.
Its looks like the partition and size have already been set and cannot be changed even after erasing the device with programmer and executing Erase all blocks command.
The partition command always reports ACCERR no matter what I do.
Is there any way to erase Data Flash IFR?

Is there anything I am doing wrong here?

Cheers

Here is a code snipet…..

#define EEE_SIZE_32    (0x39)

#define EEE_SIZE_64    (0x38)

#define EEE_SIZE_128   (0x37)

#define EEE_SIZE_256   (0x36)

#define EEE_SIZE_512   (0x35)

#define EEE_SIZE_1K    (0x34)

#define EEE_SIZE_2K    (0x33)

#define EEE_SIZE       EEE_SIZE_2K

#define DFLASH_SIZE_0  (0x08)

#define DFLASH_SIZE_8  (0x09)

#define DFLASH_SIZE_16 (0x0A)

#define DFLASH_SIZE_32 (0x0B)

#define DFLASH_SIZE    DFLASH_SIZE_0

int main(void)

{

   byte  accessError;

   byte  violationError;

   byte  readCollisionError;

   byte  commandComplete;

   byte   eeeReady = (FTFL_FCNFG & FTFL_FCNFG_EEERDY_MASK) ? 1 : 0;

   byte   ramReady = (FTFL_FCNFG & FTFL_FCNFG_RAMRDY_MASK) ? 1 : 0;

   dword  nvmSize = (SIM_FCFG1 & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT;

   dword  pfSize  = (SIM_FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;

   dword  eeSize  = (SIM_FCFG1 & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT;

   dword  depart  = (SIM_FCFG1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT;

   SIM_SCGC6 |= SIM_SCGC6_FTFL_MASK;                      // ensure flash memory clock is enabled

   // test if flash has be configured

   if (depart != DFLASH_SIZE)

   {

      // test and clear any errors

      if (FTFL_FSTAT & (FTFL_FSTAT_ACCERR_MASK | FTFL_FSTAT_FPVIOL_MASK))

      {

         FTFL_FSTAT = (FTFL_FSTAT_ACCERR_MASK | FTFL_FSTAT_FPVIOL_MASK);

      }

      // set EEPROM partition and size

      FTFL_FCCOB0 = FTFL_FCCOB0_CCOBn(0x80);                 // PMGPART - program partition function command

      FTFL_FCCOB1 = 0;                                       // not used

      FTFL_FCCOB2 = 0;                                       // not used

      FTFL_FCCOB3 = 0;                                       // not used

      FTFL_FCCOB4 = EEE_SIZE;                                // EEPROM - size code

      FTFL_FCCOB5 = DFLASH_SIZE;                             // DEPART - partition code

      FTFL_FSTAT = FTFL_FSTAT_CCIF_MASK;                     // launch command

      while(!(FTFL_FSTAT & FTFL_FSTAT_CCIF_MASK));           // wait for command to complete   

      accessError        = (FTFL_FSTAT & FTFL_FSTAT_ACCERR_MASK) ? 1 : 0;

      violationError     = (FTFL_FSTAT & FTFL_FSTAT_FPVIOL_MASK) ? 1 : 0;

      readCollisionError = (FTFL_FSTAT & FTFL_FSTAT_RDCOLERR_MASK) ? 1 : 0;

      commandComplete    = (FTFL_FSTAT & FTFL_FSTAT_MGSTAT0_MASK) ? 1 : 0;     

      // set flex ram as EEPROM

      FTFL_FCCOB0 = FTFL_FCCOB0_CCOBn(0x81);                 // SETRAM - set FlexRAM function command

      FTFL_FCCOB1 = 0x00;                                    // make FlexRAM available for EEPROM command

      FTFL_FSTAT = FTFL_FSTAT_CCIF_MASK;                     // launch command

      while(!(FTFL_FSTAT & FTFL_FSTAT_CCIF_MASK));           // wait for command to complete      

      accessError        = (FTFL_FSTAT & FTFL_FSTAT_ACCERR_MASK) ? 1 : 0;

      violationError     = (FTFL_FSTAT & FTFL_FSTAT_FPVIOL_MASK) ? 1 : 0;

      readCollisionError = (FTFL_FSTAT & FTFL_FSTAT_RDCOLERR_MASK) ? 1 : 0;

      commandComplete    = (FTFL_FSTAT & FTFL_FSTAT_MGSTAT0_MASK) ? 1 : 0;

}

   while(!(FTFL_FCNFG & FTFL_FCNFG_EEERDY_MASK));         // wait for EEPROM ready

[julian_morrison]

Having returned to this problem of DEPART = 0x0B after mass erase using P&E micro multilink universal I thought I would try upgrading from CW10.4 to CW 10.6. Bingo! DEPART is now erased to 0x0F and programming partition now works just fine. I thought I would share this :-)

[julianmorrison]

Thanks, I was wondering about that part.

However, I still cannot run the partition command without a ACCERR even after erasing the whole device.

Is this a 'write once' command that can only be done on a brand new device?

[Hui_Ma · Accepted solution]

Hi,

The program partition command can only execute only once during the entire lifetime of a given application.
If you want to run program partition command again, it need to do a erase all blocks command or using external JTAG debugger to do a mass erase.
Kinetis 100MHz product provides an Flexmemory example demo, you could refer that application:
[flexmem_demo] of KINETIS512_V2_SC:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=K10_100&nodeId=01624698C9DE2DDD8B&fps...

It also need pay attention that the program partition command need to be run from SRAM, not from Flash.
You can refer AN4695 file about  how to execute Flash command from SRAM:
http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf
Wish it helps.

B.R.

Ma Hui

[julianmorrison]

Thanks for the information. I understand about running from sram but I still don't understand why DEPART reports 0x0B even after jtag device erase or erase all blocks.

I am expecting it to report 0x0F.

[rogerfl]

I also am using the PE USB-ML-Universal and have seem the same problem. Just reported it in another thread. My code worked on OpenSDA but fails using Multilink in Jtag mode. See a 0x0b when I expect 0xf for DPART.

Roger

[Hui_Ma]

If the issue is same with below thread, with it helps.

https://community.freescale.com/thread/317178

[marcbunyard]

I am also using the PE USB-ML-Universal, and I'm seeing the exact same thing.  I completed running the Erase All Blocks code, but this is discouraging.  I would think the debugger could erase the FlexNVM, and allow development to simulate working with a new part. ???

[Hui_Ma]

Hi,

That's really strange. I do a test with TWR-K20D50M board, which is using PK20X128VLH  mask set "1N86B" product, which after JTAG tool mass erase operation  SIM_FCFG1 [DEPART] bits value is 0xF. How many chips with that behaviours?

[julianmorrison]

Hi Hui_Ma,

Thank you so much for your help and patience!

The JTAG programmer I am using is a PE USB-ML-UNIVSAL.

It appears that this programmer does not reset the SIM_FCFG1 [DEPART] bits to 0xF as expected. But I will investigate further.

However, I have discovered an advanced option in the programmer connection that allows me to set the EEPROM size and partition correctly and this is enough for me to move forward with our development.

I will work on programming the partition from SRAM in the near future

[KeithL]

Hi Julian -  I'm in the same situation here.  I was looking for the advanced option in the programmer connection to set the partition info. that you spoke of, but I was unable to find it.  Can you tell me where you found it? 

Thanks,

Keith

[marcbunyard]

I think you're talking about Run->Debug Configurations ->Main:Connection:Edit->Connection:Advanced Programming Options->Partition:Enable partitioning for the device.

[Hui_Ma]

Hi,

After execute the Program Partition Command, there is no need to execute Set FlexRAM Function Command.

When partitioned for EEPROM, the FlexRAM is typically used to store EEPROM data.

Wish it helps.

B.R.

Ma Hui