Potential Problem with MCGFFCLK in K64, K65, K66

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Potential Problem with MCGFFCLK in K64, K65, K66

361 Views
mjbcswitzerland
Specialist V

Hi All

I haven't been able to use MCGFFCLK from the slow clock on these part, although it works from the divided FLL external clock.

pastedImage_1.png

Here I have IREFS set to '1' but there is no output on MCGFFCLK (that is, peripherals clocked from it don't count). The slow clock is available as shown by the physically measured 32.8kHz on the CLKOUT pin.

On a K64 I have 50Mhz external clock divided by 1024 at the non-selected input to the FLL and, as shown in the next diagram where I simply set IREFS back to '0'

pastedImage_2.png

the internal peripherals on MCGFFCLK are correctly clocked (and count) at 24.4kHz.

The design is different to other parts with the "Sync" block having three inputs, one from the FLL input, one from the external reference input divided by 2 and one from the bus clock (60Mhz in both cases).

Presumably the clock is not being gated out due to the clock valid bit not being set.

Therefore:
- why does the 48kHz external clock input work but the internal 32.8kHz not?
- what would cause the clock validity check to not allow it? (Adjusting the external reference clock divide didn't change anything)
- is there some trick needed that is not described in the manual?
- has the operation been verified?

Regards

Mark

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111 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Please notice:

This clock is synchronized to the peripheral bus clock and is valid only when its frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high.

Please configure MCGOUTCLK to a higher frequency

25.4.5 MCG Fixed Frequency Clock.png

Best Regards,

Robin

 

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111 Views
mjbcswitzerland
Specialist V

Robin

I have 120MHz for MCGOUTCLK (my diagrams are wrong - I thought I was showing the CLKOUT [which is set to IRC 32kHz to verify that it is oscillating]).

Therefore 32kHz < 120MHz/8 [32kHz < 15MHz]

Since there is no problem with 48kHz (also < 15Mhz and > IRC 32k) I still don't see why 48kHz is valid but 32kHz is not.

Regards

Mark

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111 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Mark,

Have you check the value of MCG_S[IREFST] after set MCG_C1[IREFS]?

MCG_S[IREFST].png

Which MCG mode are you testing with IREFS set to '1'? 

How did you configure 120MHz for MCGOUTCLK? When PEE mode is selected, the IREFS shoud be set to '0'.

imageFile.png
I am using FEI mode and select MCGFFCLK(32.768kHz IRC) as FTM clock source, the FTM is able to output PWM.

Please select the MCG mode which IREFS=1, and then test if the FTM module is able to work.

Best Regards,

Robin

 

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mjbcswitzerland
Specialist V

Hi Robin

When I set IREFS I see the value correctly reflected in IREFST.

MCGOUTCLK is from the PLL at 120MHz.

In this state I can change IREFS between 0 and 1 without affecting the PLL operation (which may contradict the PEE requirement). With IREFS at 0 the FTM operates from MCGFFCLK; with IREFS at 1 the FTM doesn't operate (although 32kHz IRC is oscillating as measured on CLKOUT pin).

I will try with other MCGOUTCLK configurations to see whether there is a restriction in PEE.

If you have a working binary for FRDM-K64F or FRDM-K66F could you post it so that I can load it and compare?

Thanks

Mark

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