Port Digital Filters on Kinetis MK10DX256VLH7

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Port Digital Filters on Kinetis MK10DX256VLH7

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andrewparlane
Contributor IV

Looking at the MK10DX256VLH7 reference manual there are a few references to a Passive Filter / Digital Filter on input pins.

Section 5.7.4 PORT digital filter clocking, has a diagram that references a PORTx_DFCR[CS] register bit.

Section 10.2.1 Port control and interrupt module features, states: "The digital filter is configurable from 1 to 32 clock cycles when enabled".

Section 11.14.1 Pin Control Register n (PORTx_PCRn), for the PFE field states: "This bit is read only for pins that do not support a configurable passive input filter.", this suggests that it's not supported on all pins?

However there is no DFCR register in the PORT memory map.

The datasheet references the digital filter but only in terms of assuming it's disabled for given timing values.

The sample code I got for this chip via support ticket #00288369, has a DFCR entry in "struct PORT_MemMap", with the comment that it is at offset 0xC4. There is also note of DFER and DFWR registers, which again are not memory map in the reference manual.

So my questions are:

1) Does the MK10DX256VLH7 support digital filters? On which pins?

2) Where can I get information on how to configure this feature, and how it works?

Thanks,

Andrew

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi andrewparlane,

  Do you mean this one?

typedef struct PORT_MemMap {
uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} volatile *PORT_MemMapPtr;

 

If yes, it is caused by the header file, the code which I share with you is not the directly K10 72Mhz, it is just for your reference.

You need to use the K10 72Mhz header file:MK10D7.h

I attach one which I find it from the IAR install path:

C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\inc\NXP

Although the IAR related header file still have the DFCR, but from the K10 72Mhz reference manual, we can find there are no DFCR register, so the K10 72Mhz should don't have this register function.

You can ignore the DFCR, and don't use the filter function.

Now answer your questions:

1) Does the MK10DX256VLH7 support digital filters? On which pins?

Answer: As the RM don't have the filter register, you can consider that the pin can't support the digital filter function.

2) Where can I get information on how to configure this feature, and how it works?

Answer: The K10 72Mhz can't support this function, but K10 120MHz can support the filter function.

Best Regards,

Kerry

 

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andrewparlane
Contributor IV

OK, Thanks for the info,

 

Andrew

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi andrewparlane,

  Do you mean this one?

typedef struct PORT_MemMap {
uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} volatile *PORT_MemMapPtr;

 

If yes, it is caused by the header file, the code which I share with you is not the directly K10 72Mhz, it is just for your reference.

You need to use the K10 72Mhz header file:MK10D7.h

I attach one which I find it from the IAR install path:

C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\inc\NXP

Although the IAR related header file still have the DFCR, but from the K10 72Mhz reference manual, we can find there are no DFCR register, so the K10 72Mhz should don't have this register function.

You can ignore the DFCR, and don't use the filter function.

Now answer your questions:

1) Does the MK10DX256VLH7 support digital filters? On which pins?

Answer: As the RM don't have the filter register, you can consider that the pin can't support the digital filter function.

2) Where can I get information on how to configure this feature, and how it works?

Answer: The K10 72Mhz can't support this function, but K10 120MHz can support the filter function.

Best Regards,

Kerry

 

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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