Poor sigma delta ADC resolution [MKM34Z]

[zbigniew_halat]

Hardware:

TWR-KM34Z75M

Software setting:
According to "KM Family Reference Manual"  

• S&D adc is clocked by 6.144 MHz clock generated from PLL with 32.768 kHz
• no others module is using this clock to fulfill reference hint:
  

  'When PLL is driving AFE clock, this clock should not be used for any other module including the core, bus, flash and other peripherals as this is necessary to ensure good accuracy from AFE.'

• continous conversion mode
• pga gain disabled
• oversampling: kAFE_DecimatorOversampleRatio1024
  
  

Test:

Just short differential input together [EXT_SD_ADPx to EXT_SD_ADMx;  where: x = 0 .... 2], run conversion and get multiple samples.

The expectation is that:

• the average value will be DC-offset. (Perfectly 0)
• the variance tells about resolution (Perfectly variance shall be 0). The higher variance the lower resolution.
  
  

Results:

Here is a result from the first S&D 24 bits converter. I took it from 40 samples

[15:25:14:034] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101010101001␍␊
[15:25:14:034] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101101011000␍␊
[15:25:14:034] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100110000010111␍␊
[15:25:14:034] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100110011011111␍␊
[15:25:14:034] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101011100100␍␊
[15:25:14:034] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101011001111␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101011011010␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101100111010␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101100010010␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101010110110␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101100101111␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100110001100001␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100110011000010␍␊
[15:25:14:079] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101110011011␍␊
[15:25:14:123] LOG_LEVEL_INFO: #LOG_LEVEL_DEBUG: 111111111100101110011110␍␊

...

val_max-val_min = 909. It tells that about 10 bits are useless (2^10>909).
So because S&D has 24bit resolution, we can say that ENOB (effective number of bits) is 24- 10 =14bits.
Take a look at the samples, its clear to see that the LSB bits are trash.
I have done such test many times and always get the same results ENOB: 12-14bit.

Question:

Why MKM34Z's S&D adc has such poor resolution?
Is there any trick to increase the resolution??

[FelipeGarcia]

Hello,

You could take a look to the below document to increase accuracy of an ADC.

https://cache.nxp.com/docs/en/application-note/AN5250.pdf

Hope it helps!

Best regards,

Felipe