PWM generation in MKV31F512VLL12

[HARINI_T]

Hi @EdwinHz,

Earlier we had discussions regarding the auto updation of the duty cycle into the registers. And that issue got solved using the SetSoftwareTrigger function as instructed by you. Now, I am now facing a few issues if the code is inside the while loop. Without the code inside the while loop, the output is obtained as per the table I have mentioned in my previous query (I have also attached it in here below). But if I put the code inside the while loop, I am unable to generate the desired signal. The auto-updating of registers is ensured but not the output generation. 

Input 1	Input 2	Input 3	PWM o/p
GPIOB 1	GPIOB 10	GPIOB 2	Channel 0	Channel 1	Channel 2	Channel 4	Channel 5	Channel 6
0	0	1	1	Disabled	Disabled	Disabled	Disabled	1
0	1	0	Disabled	1	Disabled	1	Disabled	Disabled
0	1	1	Disabled	1	Disabled	Disabled	Disabled	1
1	0	0	Disabled	Disabled	1	Disabled	1	Disabled
1	0	1	1	Disabled	Disabled	Disabled	1	Disabled
1	1	0	Disabled	Disabled	1	1	Disabled	Disabled

1. The PWM output is not achieved from the desired pins; instead I am observing a logic high output without any PWM pulses. i.e. Let's take the first case of having inputs 1, 2 and 3 as logic 0, logic 0 and logic 1 respectively. So we expect an output of a PWM generation at channels 0 and 6 and the rest of the channels are expected to generate 10kHz PWM signal haing 2 percent duty cycle. But we observe only a logic high signal from the channel 0 and channel 6 pins and the rest other pins generate a PWM output with a random duty cycle value of 10 percent or 16 percent, which I havent set. The set value is 2 percent but the output is deviated from this value. 
2. The frequency of the PWM pulses from channels 1, 2, 4, 5 are set at 10kHz but the output is obtained at 100kHz or even greater than that. Please help me debug this issue. I have also attached the code herewith together with the images for your reference. 
3. I recently changed the code so that the update of duty cycle happens only when an interrupt occurs so as to reduce the frequency of the PWM pulses from 100kHz to 10 kHz (which is desired). But the frequency didn't get reduced and instead has been slightly lowered to 90kHz. 

Figure 1. 3.3V output from the pins which need to produce PWM pulses. 

Figure 2. PWM pulses from the undesired pins having 20 percent duty cycle and 100kHz frequency. 

Please help in debugging this issue @EdwinHz!

[EdwinHz]

Hi again, @HARINI_T!

I see your while look is constantly polling for the status of the three GPIO inputs, and updating the PWMs accordingly. When you mention:

“Without the code inside the while loop, the output is obtained as per the table”, where would you place the trigger, if at all? Do you mean you would only do a single trigger, the output would be reflected, and then no update would be done and the PWM configurations would be soft-locked into a single state?

I believe the polling might be being done a little bit too often, not giving the trigger enough time to properly update all of the registers and ending up with unexpected results like the ones you mention.

The better solution would be to update the PWMs and generate a trigger, only when a GPIO changes (interrupt based solution) instead of constantly polling the GPIOs and creating triggers to fast (current implementation). This way, you ensure that the register buffers get enough time to refresh their values and set them properly on the FTM module without mistake.

BR,

Edwin.