PIT->PDB->DMA

[ishwarlal]

Hi,

We are using MK66 with a custom board, AtollicTs no sdk (custom code) .

I am looking for an example to for PDB to trigger DMA transfer. There is a lot of discussion related ADC trigger DMA and PIT trigger DMA and PDB trigger ADC in forum but no post related to PDB trigger DMA.

Actually I want to trigger DMA_CH0 & DMA_CH3 with PIT0 the first part is easy PIT0 is internally connected to DMA_CH0 but the second part is tricky, I tried it myself but no success. the first part is working (i-e PIT0 trigger DMA_CH0) but the second part is not working (i-e PIT0->PDB->DMA_CH3). My all other PIT channels are already used for other tasks.

Dose anyone know have experience with PDB DMA trigger?

Regards

Lal

[ishwarlal · Accepted solution]

Ok I solved the problem it was due to IDLY register, the IDLY is set to 0xFFFF by default and this is to large in my case, I simply set it to 0 and it works.

Here is the PDB code:

   SIM->SCGC6 |= SIM_SCGC6_PDB(1);
   PDB0->SC = PDB_SC_LDMOD(3) | PDB_SC_PRESCALER(0) | PDB_SC_TRGSEL(4) | PDB_SC_MULT(0) |    PDB_SC_DMAEN(1) | PDB_SC_CONT(0);
   PDB0->IDLY = 0;
   PDB0->SC |=  PDB_SC_PDBEN(1) | PDB_SC_LDOK(1);

Regards

Lal

[ishwarlal]

In case someone also need the DMA code, here it is:

volatile DMA_Type*    m_pDma = DMA0;
const uint8_t  m_Ch = 3;
uint16_t SrcDataBuff[2];
uint16_t DestData;

void Init_Dma()
{
    //Enable clocks
    SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
    SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;

    m_pDma->CR |= DMA_CR_HOE(1)          //DmaHaltOnErr(true)
                | DMA_CR_EDBG(1)         //DmaHaltOnDbg(true)
                | DMA_CR_ERGA(1)        //DmaSetGroupAribt(RndRobin)
                | DMA_CR_ERCA(1)        //DmaSetChannelAribt(RndRobin)
                
    m_pDma->TCD[m_Ch].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_SMOD(0) | DMA_ATTR_DSIZE(1) | DMA_ATTR_DMOD(0);

    //Here put correct source and destination address parameters.
    m_pDma->TCD[m_Ch].SADDR =   SrcDataBuff; //Source address
    m_pDma->TCD[m_Ch].SOFF  =   2;             //Source offset
    m_pDma->TCD[m_Ch].SLAST =  -4;             //Source final address adjustment.

    m_pDma->TCD[m_Ch].DADDR     = &DestData;  //destination address
    m_pDma->TCD[m_Ch].DOFF      = 0;
    m_pDma->TCD[m_Ch].DLAST_SGA = 0;

    //number of bytes to transfer per dma request
    m_pDma->TCD[m_Ch].NBYTES_MLNO = 2;

    //Dma major iteration count
    m_pDma->TCD[m_Ch].BITER_ELINKYES |= DMA_BITER_ELINKYES_BITER(2); //2 iterations
    m_pDma->TCD[m_Ch].CITER_ELINKYES = m_pDma->TCD[m_Ch].BITER_ELINKYES

    //Enable hardware trigger so that PDB can trigger DMA
    m_pDma->SERQ = m_Ch;    //enable hw triggering.
    DMAMUX->CHCFG[m_Ch] = 0;
    DMAMUX->CHCFG[m_Ch] = DMAMUX_CHCFG_ENBL(1) | DMAMUX_CHCFG_SOURCE(48); //Select PDB as hw trigger source.

    //at this point you may enable DMA Interrupt.
}