Operation of an unprogrammed MK10DN512ZVLQ10 coming out of a POR.

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Operation of an unprogrammed MK10DN512ZVLQ10 coming out of a POR.

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markbrinkman
Contributor II

Does anybody know what kind of waveform I should be seeing on a blank MK10DN512ZVLQ10 "reset" pin after a POR? I assume a continuous stream of watchdog timeouts but how long is it active LO and how long is it inactive HI?

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Mark:

You are correct that an oscillating reset pin is observed in blank devices. However I do not think it is simple to determine the High/Low times. Moreover, the waveform depends on your external circuitry. e.g. if the pin is floating you will see a pulse-train signal, but if you have an external capacitor you will instead see a charging signal followed by an abrupt fall to ground and again.

Regarding the reset cause, instead of the watchdog, I think this is caused by the CPU trying to execute code from an illegal address. First thing after a reset, the CPU loads the Program Counter with the reset vector loaded at address 0x4. This vector contains a 0xFFFF_FFFF in erased state. CPU tries to "jump" to address 0xFFFF_FFFF and this causes the reset.


Regards!,
Jorge Gonzalez

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Mark,

As you know, the RESET pin is an input pin, which is one of Reset source and can reset the chip as the other Reset sources do for example POR. The MK10 chip do not have reset output pin, you can not see the Reset output waveform. When the MK10 is blank, it can output nothing.

BR

XiangJun Rong

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markbrinkman
Contributor II

Hey XiangJun,

Thanks for the response but the documentation states otherwise. Section 5.1.2.4 of the KQRUG R3 user's guide states "The reset pin is driven out if internal circuitry detects a reset." and later describes that customer's should not connect to the reset pin if they do not want external circuitry to reset. This is reiterated in document number K10P144M100SF2V2RM section 6.3.4 and other places (section 10.4.2 states RESET is a bi-directional signal). In addition it also states that it is driven for ~128 bus clock cycles. This spec. should be in the data sheet. However, I don't believe the 128 bus clock cycles applies to reset pin after powering up a blank device. According to my scope reset has a 50us pulse rate with 96% active LO duty cycle.

Mark

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Mark:

You are correct that an oscillating reset pin is observed in blank devices. However I do not think it is simple to determine the High/Low times. Moreover, the waveform depends on your external circuitry. e.g. if the pin is floating you will see a pulse-train signal, but if you have an external capacitor you will instead see a charging signal followed by an abrupt fall to ground and again.

Regarding the reset cause, instead of the watchdog, I think this is caused by the CPU trying to execute code from an illegal address. First thing after a reset, the CPU loads the Program Counter with the reset vector loaded at address 0x4. This vector contains a 0xFFFF_FFFF in erased state. CPU tries to "jump" to address 0xFFFF_FFFF and this causes the reset.


Regards!,
Jorge Gonzalez

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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