Open Drain on K20 (MK20DXxxxVLL7)

[stevenjohnson]

This question has sort of been asked before relating to other processors in the Kinetis family, but the answers do not specifically apply to this device line (and the answers implied they might be chip specific), and the two replies had differing advice, one implying it couldn't be done, the other that it could, so for the sake of clarity i am re-asking the question and hoping to get a definitive answer.

In the questions assume the following arrangement, a GPIO controlled peripheral line with an external pull up to a 5V supply line, processor is operating at 3.3V.

Q1: On the K20, are ALL GPIO able to be Open Drain?

Q2: Are the GPIO when set up for Open Drain TRUE Open Drain, or Pseudo Open Drain?

Q3: If i have a pull up to 5V and the GPIO on the K20 set to Open Drain, will the line pull to 5V when the output is set to 1, or is it limited by protection rails inside the chip? 

Q3.1 If limited, is this mode detrimental to the chip? (Output Open Drain with a 5V pull up)

Q4: Can i simulate True Open Drain setting the port as output/open drain, with the output set as 0.  And then toggle direction to control the pin. (Input logic high 5V pull up, Output logic low driven) 

Q4.1 If the Pin is set as an Input will the line pull high to 5V or is it restricted by protection rails inside the chip when configured as an Input?

Q5: Can I simulate True Open Drain by disabling the pin (for a logic one pulled to 5V), and enabling the Pin as GPIO (with the GPIO preconfigured as an output low, for logic zero)

Do the answers to Q2 thru Q5 remain true for all Kinetis K series processors or is it different for different chips?

[soledad]

Q1: On the K20, are ALL GPIO able to be Open Drain?

ANSWER.  Yes, you can review  the register PORTx_PCRn,  bit ODE in order to enable this functionality remember that this pins are pseudo Open Drain.

Q2: Are the GPIO when set up for Open Drain TRUE Open Drain, or Pseudo Open Drain?

ANSWER.  Pseudo Open Drain

Do the answers to Q2 thru Q5 remain true for all Kinetis K series processors or is it different for different chips?

ANSWER.

All Kinetis K family MCUs so far have clamping diodes to VDD

& VSS on all GPIO except true open-drain pins. (IIC, UART).  This allows positive and

negative current injection for applications like this. The current injection spec

limit is 2mA per pin, but it’s a good practice to keep it an order of magnitude

lower. As long as the injected current is limited there aren’t any concerns.