OS Time Change in SleepMode

[somesh_malla]

Hi,

In my project we configured different frequencies as below for MK20FX512VMD12

• Y1 = 16 MHz crystal oscillator
• Load capacitance set by OSA0_CR registers = 10 pF
• Clock input is selected to EXTAL0 (16MHz)
• PLL pre-divider = 2, multiplier = 30
• OUTDIV1 = 0 OUTDIV2 = 1 OUTDIV3 = 2   OUTDIV4 = 5

Module Clocks

• PLL = 240 MHz (16 MHz / 2 * 30)
• MCGOUTCLK = PLL / 2 = 120 MHz
• Core Clock = MCGOUTCLK / OUTDIV1 (0) = 120 MHz
• Bus Clock = MCGOUTCLK / OUTDIV2 (1) = 60 MHz
• FlexBus Clock = MCGOUTCLK / OUTDIV3 (2) = 40 MHz
• SRAM Clock = MCGOUTCLK / OUTDIV4 (5) = 20 MHz

MCG_C1 0x20 (External reference clock is selected)

Enabled the sleep mode by setting the LPTMR TEN and TIE bits of LPTMR register

Low Leakage Stop Mode in SMC_PMCTRL register

SLEEPEEP bit in System Control Register

After WFI instruction it waits for interrupt, after this point what is the system/core clock frequency?

As it was configured to use external reference clock in low power mode can I consider 16MHz as the clock used as System/Core clock during this sleep mode?

But from the reference manual it is given as System/Core clock will become divide by 8, which is correct? does it uses external reference clock or it divides the frequency by 8 for computation?

Please see https://community.nxp.com/t5/Kinetis-Microcontrollers/OS-Time-Change-after-coming-out-from-SleepMode... for more details.

Regards,

Venkata

[danielchen]

Hi @somesh_malla :

The RTOS tick is the operating system time unit. RTOS measures time in ticks, instead of in seconds and milliseconds.   Which RTOS you are using?  FreeRTOS or MQX RTOS?

Regards

Daniel

[somesh_malla]

Hi Daniel,

We are using Micrium RTOS, Also attached the register settings read in normal mode and low power mode.

	Normal Mode	Low Power Mode	Normal Mode	Low Power Mode
MCG_C1	00100000	00001110	FRDIV=16 External reference clock is selected.	FRDIV=2 Slow Internal Reference clock is selected Internal Reference Clock Enable Internal Reference Stop Enable
MCG_C2	10010100	00000111	High frequency range selected for the crystal oscillator FLL or PLL is not disabled in bypass modes Slow internal reference clock selected.	Low frequency range selected for the crystal oscillator FLL or PLL is disabled in bypass modes (lower power) Fast internal reference clock selected
MCG_C5	00000001	10000000	Selects OSC0 clock source as its external reference clock PRDIV0 = 2	Selects OSC1 clock source as its external reference clock PRDIV0 = 1
MCG_S	01101110	00000111	PLL0 has acquired lock. Source of PLLS clock is PLLCS output clock Output of the PLL is selected Source of internal reference clock is the slow clock (32 kHz IRC).	Source of PLLS clock is FLL clock Internal reference clock is selected. Source of internal reference clock is the fast clock (4 MHz IRC).

Regards,

Somesh