Not satisfied with noise on K22FN

[michaelheidinge]

Dear Kinetis-Team,

i have a complain about the Kinetis MCUs, K22FN512.

I did all the art for a good adc result:

1. Voltages are highly stable and noise free

2. ADC inputs are driven by ADC-Driving OpAmps

3. Reference voltage is stable.

4. Solid GND Plane

However, I get noise on my result:

Its 12 binary digits noise at 12 Bit conversion. Thats too much for me, as I want to use the adc in a control loop.

Its approx 0,2%-0,3% noise in the measurement range but this is too much for a good adc, like the datasheet promises.

What can I do better to improve my performance? I want to switch to Kinetis KV44. Will there be better results?

I'm pretty sure you won't do a new revision, but please make more sure next time, you get a good and stable adc result.

Other people also complained with similar results.

https://community.nxp.com/thread/322988 

[michaelheidinge]

Update: The KE1xF seems to have an decent ADC. Guess, I will use that part.

[Hui_Ma]

Hi

There with some suggestions about how to get better performance of Kinetis SAR ADC:

[ADC Calibration]

[Hardware Configuration]

[ADC Configuration]

There also with an application note AN4373 about SAR ADC cookbook, please check here for the detailed info.

Wish it helps.

Have a great day,
Ma Hui
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[michaelheidinge · Accepted solution]

Hi,

thanks Ma Hui for your support. I checked that I followed all the recommended steps.

What I tried and did not help:

Current state: 0.15% noise

Practically, I have the same problem as you describe in the 19 counts off example.

-Replaced switching regulator with lab power supply. Same issue.

-Vss&Vref are already highly bypassed.

-No chance to place ferrite beads in the design. However, as no more switching device is left, nor any noise can be seen with 12 bit oscilloscope, i guess this will not make a difference.

-played with sample time: No difference. ADC Channels are actively driven by opamp, so i guess this won't be an issue anyhow.

-reduce the clk divder highly. Same issue.

What helped (if you have same problem):

Changed clk source from Bus Clk to Oscillator Clock: OSCERCLK

So I recommend using OSCERCLK with 8MHz.

Now i have 0.07% noise, which meets the Freescale minimum spec of 10.4 effective bits.
How to calulate: 1/2^ENOB=0,074%

What I guess (it's just a guess, based on the made experience): The Busclock is not stable enough, has some gitter? I use standard 120MHz option for KN512. When I change the frequency from 10MHz to 5MHz same issue.

In case everything else fails:

Oversampleing and averaging.

Generally I would like to have a more stable adc.

[michaelheidinge]

Just checked with the datasheets: The ADC of the Kinetis just seems so bad, as i measured.

If you look at STM parts, eg. STM32F334, they have a 10dB better SNR ADC build in. I strongly recommend to improve the ADC on the Kinetis devices.

The KV4x 4MSPS ADC gets even worse: It has 9.1 effective bits. Oversampling by a factor of 4 increases the effective bits by 1. This means that that ADC is useless in the KV4x. I need a better ADC on the KVx series!

The KV5 ADC is better, but I cannot afford double the price...