Hello again Ma Hui.
I keep trying on this and I found a rather strange issue.
Now that I know where the voltage drops come from, I see more drops than there should be. Please let me to explain myself:
In the following picture you will find my setting for the ADC component. As you can see, the conversion time results in 2.166us.

Some highlights:
- Bus clock = 24MHz.
- ADC clock = 12MHz.
- Number of conversions = 1, which means that no averaging is enabled.
In the picture below the input signal is shown. As I am working in the continuos mode, the signal is converted non stop. The cursors show 1.08us between voltage drops which means every time the sampling capacitor starts changing. It should happen every 2.16us but the osciloscope shows that is every 1.08us (suspiciously half of 2.16us)

In order to see what is going on, I decided to complement a pin every ADC conversion completed interrupt (AD1_OnMeasurementComplete).
- In the following picture the voltage drops are noted from A to F (every 1.08us).
- The square signal in dark blue shows every time a conversion is completed, and it happen to be every 2.16us !!!!!! (as PE shows)
- Delay X is assumed to be time between the end of the conversion and the complement instruction in the interrupt subroutine.
- When the conversion that corresponds to the drop A finishes, the interrupt is executed and the pin is complemented. Automatically begisns the conversion B.
- When the conversion B finishes, theres is no interrupt and the conversion C starts. It seems that the interrupts from B, D and F are missed.

Note: The disturbances are due to the pin complementing.
Having seen so strange behaviour, I decided to debug the code in order to read the ADC registers, and this was the result.

SC3 = 0X08, means:
- AVGE = 0 --> Hardware average function disabled.
CFG1 = 0x14, means that:
- ADIV (clock divde select) = 00. --> No prescaler.
- ADICLK (input clock select) = 00. --> Bus clock. ????????? :smileyconfused:
In the first picture, in the PE settings, we saw that Bus clock = 24MHz and ADC clock = 12MHz. The value of CFG1 shows that ADC is working at 24MHz and should be 12MHZ. Is there a divider missing somewhere?
However from the oscilloscope I draw the conclusion that the ADC Clock is working at 24MHz (that would be the reason of the 1.08us instead of 2.16us) and the hardware average function is enabled to make 2 samples average. Nevertheless the AVGE =0 and 4 samples average is the lowest option and not 2 samples average.
Could it be a Processor Expert bug?
Am I missing something in the conversion?
Am I missreading something about voltage drops and convesions?
I hope I explained myself properly.
Thank you in advance.