MKE04Z128VLD4 I cannot judge the power-on reset.

[jun1]

Hi.

I am using MKE04Z128VLD4.
I have a question about power-on reset.
I am in trouble because I cannot judge the power-on reset.
The SIM_SRSID register will be 0x04250002 when the CPU is powered on and started. The reset pin (PTA5) is pulled up externally with 4.7KΩ. 

1) At this time, the LVD flag is 1, but is there any reason why the POR flag is 0?
2) Also, if the LVD flag is 1 after starting the CPU, can it be regarded as a power-on reset?

This is the source code.

bool boardResetPowerOn (void)
{
　　uint32_t bl = SIM_SRSID_POR (1);
　　uint32_t srsid = (SIM-> SRSID);
　　bool result;
.
　　if ((bl & srsid)! = 0u) {// 1 Reset caused by POR
　　　result = true;
　　} else {
　　　result = false;
　　}
　　return result;
}

Thank you.

[jun1 · Accepted solution]

Thank you for your reply.

I solved it from the conclusion.
The test board was manually soldered. The board with the parts mounted on the machine came today, so when I turned it on, both the POR flag and the LVD flag were set.
It seems that it will happen due to some influence of hardware, but I was not sure.
For the time being, I solved it with a genuine product, so this matter will be closed.
Thank you very much.

jun

[myke_predko]

@jun1 

I've been waiting to see if anybody else has replied to this as I have had this requirement in the past and never found a foolproof way of resolving the issue.  

When I look at the RM for LVD (bit 1) of SIM_SRSID the RM Register/Bit description says pretty definitely that "This field is also set by POR." which means that it won't work the way you want it.  

However, might I suggest that you look at the LVWACK in the PMC_SPMSC1 register - according to the RM it comes up as 0 on POR and is set when an LVD has happened.  You would need to try this to see if it works as it seems to be described.  

Regardless, determining when an MCU is coming out of reset due to a POR or LVD event can be non-trivial.  The best way I found to handle the situation (on another device) was to monitor the Vdd level with a comparator pin (in my case using a Zener as the reference) and when Vdd dipped below what I considered acceptable but above the MCU's trip point then I handled it as an LVD event and ignored the internal "LVD"/"POR" bits in the MCU's registers all together.  

The other approach I've used (and had to convince the customer of) is to treat all resets as POR events and reset the whole system - which isn't a bad assumption becaue if Vdd has dropped to the point where the MCU resets then everything running in the system is at a suspect state.  

Good luck, let me know how it works out for you,

myke