MK64 UART5 is prone to have a receiver overrun error.

[jake111]

I'm using MK64FN1M0VMD12.On this chip,UART0~3 support bidirectional DMA channels,which means DMA_TX and DMA_RX can be used simultaneously.While UART4~5 can only choose one-direction DMA,so I implement UART5_RX to DMA channel to receive data,and call UART_WriteBlocking() to send data.

My program just do a UART-echo,PC->MK64 UART5-RX then MK64 UART5-TX->PC.The baudrate is 115200,and I send at the speed of 1000Bps.After a while,UART5 overruns.(Even if I don't use EDMA to receive,it also overruns when using the ringbuffer way in the SDK.).It can work about 10min when I set the baudrate to 38400 on UART5.But it works well on UART0 and UART1.I havn't tested UART2~4 due to hardware design.

What's the difference between UART0~3 and UART4~5.I know the difference that the clock frequency of UART0~1 is 120MHz,and UART3~5 is 60MHz,but I think 60MHz is enough.Besides,UART4~5 don't support bidirectional DMA channels,are the performance of UART4~5 not that good?such as smaller fifo.

Here is the register changes after overrunning.

UART5_S1 OR = 1

UART5_SFIFO RXOF = 1

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In the DMA receiving process,I've set the UART_RxIdle inturrupt to receive whenever rx is idle.

UART_ClearStatusFlags(base, kUART_IdleLineFlag);
UART_TransferAbortReceiveEDMA(); //abort EDMA to copy data
DMABuf_TO_ReadBuf();             //copy data to read buffer
UART_ReceiveEDMA();              //enable EDMA for next receive

I find that an overrun occurs before enabling EDMA as the code above.That is to say,new data comes when copying data.So the case that higher baudrate like 115200 will cause an overrun seem to make sense.But how can I receive when rx is idle and no overrun occurs,and why do UART0~1 work well?

[jake111]

I‘ve solved this.

the fifo depth of UART5  is only 1 dataword,while UART1 is 4 datawords.

But the fifo depth is read only,it's too small for UART5 to work even the baudrate is 38400.I have to disable the fifo.

The effect of the UART fifo is to speed up the process of data receiving.

but in the DMA mode,does it also need to have a receive fifo?

[Miguel04 · Accepted solution]

Hi @jake111 

After doing some research I found that the DMA does not need a receive FIFO, it could work getting the data directly from the UART data register.

Let me know if you have any other question.

Best Regards, Miguel.

[jake111]

Thanks for your researching,I've no other question.

[Miguel04]

Hi @jake111 

I am Miguel.

I'm glad you find a solution for your initial problem, I was investigating it. I'll look into the DMA fifo you are asking, as soon I find something I will let you know.

Best Regards, Miguel.