I'm using an MK64FN1M0VLL12 as the Chassis Manager in a System Management Bus Architecture. The System Management Bus uses (2) I2C interfaces [IPMB-A and IPMB-B]. I use Pin G11 configured as I2C0_SCL and Pin G10 configured as I2C0_SDA for the IPMB-A Interface. I use Pin C6 configured as I2C1_SCL and Pin C5 configured as I2C1_SDA for the IPMB-B Interface. The System Management Bus is Operating in Multi-Master Mode as per I2C Specification. All (4) Pins [G11, G10, C6, and C5] are configured as Open-Drain Pins. The I2C Specification sets Vol = 0.4V {Max.} @ 3mA Sink. When I look at the Electrical Characteristics in the Kentis K64F Sub-Family Data Sheet [K64P144M120SF5, Rev. 7, 11/2016] I see under Table 4 [Voltage and Current Operating Behaviors] that Vol = 0.5V {Max.} @ 9mA Sink when 2.7V < Vdd < 3.6V when I/O Pins are configured as High Drive Strength. When I configure these (4) Pins [G11, G10, C6, C5] as Open-Drain Pins, will these Pins meet the I2C Specification of Vol = 0.4V {Max.} @ 3mA Sink or will these Pins Operate with Vol = 0.5V {Max.} @ 9mA Sink when 2.7V < Vdd < 3.6V? In Summary, is there a specification for I2C Capable I/O Pins [Vol = 0.4V {Max.} @ 3mA Sink] Configured as Open-Drain, different from the GPIO Specification listed under Table 4 [Vol = 0.5V {Max.} @ 9mA Sink]? I need the additional 100mV of Noise Margin Preserved on these Pins when they are "Driving" the I2C_SCL and I2C_SDA Pins Out [0.4V as per I2C Spec. versus 0.5V which is listed in the Data Sheet].
