MK30F64VLH10 CMP Problem

[martinzhang]

Hello,

I got a problem of MK30F64VLH10 CMP with ADC module, following is the detail:

MCU:                                    MKV30F64VLH10

ADC Module:                    ADC0 and ADC1

Every second, there are 16 sampling groups, in each sampling group, there are 9 sampling points, in each sampling points, the ADC0 work in differential 16-bit mode and ADC1 work in single-ended 16-bit mode

CMP Module:                    CMP1:

Pins:

CMP1_IN1

CMP1_IN3

CMP1_OUT

Signal in CMP1_IN1: 50Hz sine wave

Signal in CMP1_IN3: Reference voltage

Issue Description:

When the ADC module is working, the output of CMP signal is getting bad that means there is a lots of output in the zero crossing point. But if disabled ADC module, the CMP output is OK.

The attached files are the signal got from CM1_OUT disabled and enabled ADC module.

Best Regards,

Martin Zhang

[xiangjun_rong]

Hi, Martin,

I think you use the same analog pin as the ADC channel and the CMP input, when the ADC channel is routed to S/H(sample/hold), the ADC channel input impedance is changed, which may change the ADC analog channel voltage.

I suggest you set the HYSTCTR bits in CMPx_CR0 as 11 in binary, which will set the hysteresis as level 3(30mV), I think the hysteresis feature will solve the problem.

BR

XiangJun Rong

[martinzhang]

You are right, I connected the pin for ADC sampling and CMP input, but I have done the test: Disabled the ADC input pin, but there is no improvement.  So I am not understand the reason you said that ‘when the ADC channel is routed to S/H(sample/hold), the ADC channel input impedance is changed, which may change the ADC analog channel voltage.’

I have already set the HYSTCTR to 3 (30mV), this can partly solve this problem. In addition I have increased the  number of CMP_CR0_FILTER_CNT, the result is better.