#define ISR(x) \
static void ISR_ ## x () \
{ \
__asm volatile ("bkpt #0\n") ; \
}
ISR(7)
ISR(8)
ISR(9)
ISR(10)
ISR(11)
ISR(13)
ISR(14)
ISR(15)
void (* const g_pfnVectors[])(void) =
{
// Core Level - CM3
(void *)&_vStackTop -1, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
ISR_7, // Reserved
ISR_8, // Reserved
ISR_9, // Reserved
ISR_10, // Reserved
// vPortSVCHandler, // SVCall handler
ISR_11,
DebugMon_Handler, // Debug monitor handler
ISR_13, // Reserved
// xPortPendSVHandler, // The PendSV handler
ISR_14,
// xPortSysTickHandler, // The SysTick handler
ISR_15,
//16
.....
I have such code and after second pass trough crt0 ISR_7 is fired. Can I safely ignore this interrupt or it shows some error in code which I should address? Reference manual of mcu says that this interrupt is reserved.
CRT0 does:
- disables interrupts
- disables watchdog
- setup stack pointer
- zero bss
- fill stack with canar value
- copy data to ram
- copy isr table to ram
- set pointer to isr table so they run from ram
- enables fpu in CPACR
- enables PORT clocks
- setups clock from external RTC clock
- NVIC_SetPriorityGrouping(0)
- goes to main function which enables interrupts