MK10 ADC input pin structure

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MK10 ADC input pin structure

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wei_xu1
Contributor II

Hi team,

I'm working on a design based on MK10DN512VLQ10, the system has several ADC inputs, now we need to protect the inputs from 32V overvoltage. Since we don't want to modify the PCB(it was designed by someone else and the we need to keep up with the schedule), I thought a current limit resistor could solve the problem and limit the current under a safe range(5mA), and the voltage will be calmped by the diode inside MCU(judged from diagram in the datasheet like below).

pastedImage_3.png

So I use a 10K resistor to protect IO from 32V over voltage, when I appllied a 32V, the clamp voltage on the pin reachs 10V instead of around 4V. I also did minus and plus 10V sweep on the analog inputs(with 10K resistor), the behaviour is just like a 5V tolerance pin and only has negative voltage clamp ability.

Is it a 5V tolerance pin and where can I find the information about all 5V tolerance pins?

Does the MCU has 10V clamp for all 5V tolerance pins and what's the structure inside?

Thanks!

Wei Xu

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1 Solution
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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

You tested pins are 5V tolerant I/O pad, which I/O pad connect diode to internal ESD bus (instead of VDD).

The ESD bus is isolated with K10 VDD power trail.

That's why you could find 10V ramp up  instead of 3.6V (VDD).

When you want to connect high voltage to those pins, which need to consider the DC injection current(+/-5mA).

Please refer below connection for an example.

pastedImage_5.png


Have a great day,
Mike

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

The analog function IO is not 5V tolerance pin.

Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.

About analog function IO, please refer below connection (voltage divider) as an example about connect higher voltage(>3.3V) input.

pastedImage_1.png


Have a great day,
Mike

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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wei_xu1
Contributor II

Hi Mike,

Thanks for your help!

But how comes the 10V? If there is a clamp diode inside just like your diagram, the maximum voltage at the pin should not exceed 4V. Below is the sweep test that I did.

pastedImage_1.png

From 0-10V, there is no clamp at all and when the voltage is above 10V, it will be clamped to 10V, I can't find any information about this from the datasheet, please help!

Thanks and regards!

Wei Xu

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

Which MCU pin you are testing with?

What's the voltage level of the red link in below picture?

pastedImage_1.png

Is that is 0V to board/K10 GND pin?


Have a great day,
Mike

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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wei_xu1
Contributor II

Hi Mike,

Sorry for lack of information.

The MCU pins are PTB03/ADC0_SE13, PTE25/ADC0_SE18,PTA07/ADC0_SE10.

The red line that you add is 0V and ground of MCU.

Thanks and regards!

Wei Xu

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897 Views
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

You tested pins are 5V tolerant I/O pad, which I/O pad connect diode to internal ESD bus (instead of VDD).

The ESD bus is isolated with K10 VDD power trail.

That's why you could find 10V ramp up  instead of 3.6V (VDD).

When you want to connect high voltage to those pins, which need to consider the DC injection current(+/-5mA).

Please refer below connection for an example.

pastedImage_5.png


Have a great day,
Mike

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------