Kinets MKL05Z32 DAC and ADC Config

[rodrigovernini]

Hi, i'm trying to maximize the sensitivity of the ADC using a  specific range of reading, between Vrefl and Vrefh, and make this range output full VSS-VDD in the DAC, for example:

Signal Range = 1V — 1.5V

Vrefl = 1V

Vrefh = 1.5V

Reading expected:

(Input) = (Reading)

0V  — 1V = 0x0 (Saturated Region)

1V — 1.5V = 0x0 — 0xFFF (Usefull Region)

1.5V — 3.3V = 0xFFF (Saturated Region)

Output Expected

(Input) = (Output)

0V  — 1V = 0V (Saturated Region)

1V — 1.5V = 0V — 3.3V (Usefull Region)

1.5V — 3.3V = 3.3V (Saturated Region)

Vrefl and Vrefh should be standard references for ADC, for full output i made DACx_C0[DACRFS] = 1.

What i got was:

Reading:

0V — 0.5V =  0x0 — 0xFFF (Usefull Region)

0.5V — 3.3V = 0XFFF (Saturated Region)

Output

0V — 0.5V =  0V — 3.3V (Usefull Region)

0.5V — 3.3V = 3.3V (Saturated Region)

So, the ouput was ok, could make full range, but couldn't make the reading in the range expected, the range was like VSS — (Vrefh-Vrefl) = 0V — 0.5V = 0x0 — 0XFFF

Maybe the low reference for ADC will be Always VSS , can someone confirm this?

Why the high reference for conversion seens to be (Vrefh - Vrefl)?

[Hui_Ma]

Hi,

The KL05 datasheet ADC module operating conditions with below requirements of VREFL and VREFH:

VREFL is fixed to VSSA.

Wish it helps.

Have a great day,
Ma Hui

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