Hi Philipp Kaar
Sorry for the late reply. According to the Reference manual for this MCU:
TFFF flag clears automatically when DMA is used to fill TX FIFO.
To clear TFFF when not using DMA, follow these steps for every PUSH performed using CPU to fill TX FIFO:
1. Wait until TFFF = 1.
2. Write data to PUSHR using CPU.
3. Clear TFFF by writing a 1 to its location. If TX FIFO is not full, this flag will not clear.
I made some test and SPIx_SR[TFFF] is successfully clearing after 4 writes in the TX FIFO, so could you share how you write and check that this flag is not clearing to try to find your problem?
An important consideration to take with this flag is that TFFF take is cleared just when the buffer is filled, but if you have started transfers, every time you write to the SPIx_PUSHR register, the data will be shifted. Hence, it is important that meanwhile you write to the TX FIFO register you have stopped transfers. Here is part of my code of how I wirte to the register:
SPI0_MCR |= SPI_MCR_HALT_MASK;
char Master_TXval[4] = {0xB,0xC,0xD,0XE};
Master_send(Master_TXval);
SPI0_MCR &= ~SPI_MCR_HALT_MASK;
Where
void Master_send(char * mstr_val)
{
char i=0;
while((SPI0_SR & SPI_SR_TFFF_MASK))
{
SPI0_PUSHR = mstr_val[i++] | SPI_PUSHR_CTCNT_MASK | SPI_PUSHR_PCS(0x01);
SPI0_SR = SPI_SR_TFFF_MASK;
}
}
Hope this information help you.
Have a great day,
Jorge Alcala
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