Kinetis KE14Z MCU 12-bit ADC

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Kinetis KE14Z MCU 12-bit ADC

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qinshengli
Contributor I

The AD conversion speed of  the Kinetis KE14Z is supposed to be up to about 1 us, but I can only get about 5 us in

12-bit resolution. What could be the problem? I'm using the bus clock (24 MHz).

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Qinsheng,

Have you try to calculate the total conversion time according to the '36.5.4.5 Sample time and total conversion time' in KE1XZP100M72SF0RM?

36.5.4.5 Sample time and total conversion time.png

The 1200Ksps ADC conversion rate is for 10-bit mode(No ADC hardware averaging Continuous conversions enabled, subsequent conversion time)

ADC conversion rate.png

Best Regards,

Robin

 

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qinshengli
Contributor I

Hi Robin,

Thanks for your reply.

From chapter 36.5.4.5 Sample time and total conversion time:

ADC TOTAL CONVERSION TIME = Sample Phase Time (set by SMPLTS+1) + Hold

Phase (1 ADC Cycle) + Compare Phase Time (8-bit Mode=20 ADC Cycles, 10-bit

Mode=24 ADC Cycles, 12-bit Mode=28 ADC Cycles) + Single or First continuous time

adder (5 ADC cycles + 5 bus clock cycles)

default SMPLTS is 12,

I can get:

For 12-bit, Total ADC cycles = 13 + 1 +28 + 5 + 5 = 52

For 10-bit, Total ADC cycles = 13 + 1 +24 + 5 + 5 = 48

My bus clock frequency is 24 MHz (this is the spec for KE14Z), -->

the total conversion time for 12-bit is: 52 * (1/24000000) = 0.000002167 sec = 2.167 us. (The actual conversion time I measured is only 5.5 us, much slower than 2.167 us.)

the total conversion time for 10-bit is: 48 * (1/24000000) = 0.000002 sec = 2 us

It looks like if I use the bus clock for ADC clock, I cannot get the 1 us conversion time even with 10-bit resolution.

Also the measured conversion time is much longer than the calculated conversion time.

Best regards,

Qinsheng

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Qinsheng,

Continuous conversions enabled\ subsequent conversion time

You need to decrease the 'Single or First continuous time  adder':

The ADC TOTAL CONVERSION TIME =  Sample Phase Time (set by SMPLTS+1) + Compare Phase Time (12-bit Mode=28 ADC Cycles) + Single or First continuous time adder (5 ADC cycles + 5 bus clock cycles)

default SMPLTS is 12

For 12-bit, Total ADC cycles = 13 + 1 +28 + 5 + 5 = 52 42

The actual conversion time you measured should be about 1.75us.

Please check the value of SCG_LPFLLDIV[LPFLLDIV2] and set the ADC in Continuous Conversion mode(ADCx_SC3[ADCO]=1)

SCG_LPFLLDIV[LPFLLDIV2].png

And measure the "Voltage drops at ADC input during sampling process" to test the ADC conversion rate.

Voltage drops at ADC input during sampling process.png

Best Regards,

Robin

 

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qinshengli
Contributor I

Hi Robin,

Thanks for your reply.

For my application I cannot use the continuous mode. Also I’m using the bus clock as the ADC clock and as a result the SCG_LPFLLDIV[LPFLLDIV2] should not affect the ADC clock.

Best regards,

Qinsheng

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Robin_Shen
NXP TechSupport
NXP TechSupport

I am afraid you have select the SOSC_CLK as the ADC clock.

Clocking Diagram.png

PCC_ADC0[PCS].png

The frequency of SOSC_CLK depends on the external crystal oscillator.

The frequency of FLL_CLK may faster than SOSC_CLK.

You can have a try to select the FLL_CLK as the ADC clock:

CLOCK_SetIpSrc(kCLOCK_Adc0, kCLOCK_IpSrcLpFllAsync);//LPFLL async clock

Best Regards,

Robin

 

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qinshengli
Contributor I

Hi Robin,

Thanks for your replay.

I tried to use the FLL_CLK as ADC clock with LPFLLDIV2 = 2, --> the ADC clock frequency should be 36 MHz.

And then I measured the AD conversion speed and it is 3 times as fast (about 1.9 us) as before.

(When I use the bus clock (24 MHz) as ADC Clock, the AD conversion speed is about 5.7 us.)

My question is: 36 MHz is only 1.5 times of 24 MHz; however the AD conversion speed is 3 times as fast as before.

What can cause the differences?

Best regards,

Qinsheng

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Robin_Shen
NXP TechSupport
NXP TechSupport

I don't know how you select the bus clock as the clock source for fADCK. The bus clock is for the registers of ADC module.

fADCK.png

There are only four clock sources can be selected as fADCK:

00 Alternate clock 1 (ADC_ALTCLK1)
01 Alternate clock 2 (ADC_ALTCLK2)
10 Alternate clock 3 (ADC_ALTCLK3)
11 Alternate clock 4 (ADC_ALTCLK4)

ADCx_CFG1[ADICLK].png

ALTCLK2~4 are not connected on this chip. So you can only select 'Alternate clock 1 (ADC_ALTCLK1)' as fADCK.

ADC Clocking.png

There are only four clock sources for 'Alternate clock 1 (ADC_ALTCLK1)' which act as fADCK:

FLL_CLK

SOSC_CLK

SIRC_CLK

FIRC_CLK

Clocking Diagram.png

If you configure PCC_ADC0[PCS]=001 - System Oscillator Bus Clock. Then SOSC_CLK is selected as fADCK.

The frequency of SOSC_CLK is depends on the external crystal. I am not sure if you are using 24MHz crystal.

Best Regards,

Robin

 

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qinshengli
Contributor I

Hi Robin,

Thanks for your reply.

From the chart you sent to me, the frequency of SOSC_CLK depends on the external crystal. The EXTAL frequency on my board is 8 MHz, only 1/3 of 24 MHz. And this explains why my measured conversion speed is about 6 us instead of 2 us as calculated.

Best regards,

Qinsheng

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wayne_wang
NXP Employee
NXP Employee

@yonggang.chen@nxp.com

please take this issue.

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