Kinetis K70 core watchdog ISR

[mataylor]

Hello,

I am having trouble successfully running my ISR that is tied to the internal core watch dog interrupt. The device is resetting after the watch dog times out, but the break point in the ISR is never hit. I am developing with a Kinetis K70, MQX v3.8, and IAR IDE.

So far I have verified that the IRQRSTEN flag is set in the STCTRLH register. I have moved the interrupt vector table to RAM by modifying the .icf file and I moved the watch dog source code including the ISR to fast ROM. The application is using MQX version 3.8 and the _int_install_kernel_isr call to install the ISR. I have verified that _int_install_kernel_isr returns successfully and that the RAM vector table is updated with a pointer to the watch dog ISR function.

My suspicion is that I am not reaching the ISR within 256 bus clocks after the time out, but I am not sure how else to speed up the ISR request other than the steps listed above.

I would greatly appreciate any help with this issue.

[konrada]

I've never seen breakpoints work in the WDOG ISR, even when the WDOG ISR was reached. You could, however, write a magic number to one of the RFVBAT registers from within your ISR; the VBAT register file should survive resets.

[mataylor]

Thanks for the suggestion I added code to write to RFVBAT_REG0 and verified that the ISR is not being reached. 

[ignisuti]

I'm using the K10 and had similar issues.

Did you enable the Watchdog interrupt in the ARM core? This was a gotcha for me that don't think is documented very well (or at all) in the referrence manual.

Here is my code:

/* =================================================================================================  FUNCTION DESCRIPTION:==      Enable specified interrupt vector number.====  OUTPUTS:==      N/A== =============================================================================================*/void ARM_CORTEX_M4__enable_interrupt  (  IRQInterruptIndex vector  )    {    /* Local Variables. */    u8 irq;    u8 nvic_reg;        /* Check for invalid input values.      * See Table 3-4. */    if( vector < 16 || vector > 119) { printf("\nERROR: Invalid Vector value provided!\n"); return; }        /* Calculate IRQ number. */    irq = vector - 16;        /* Determine which of the NVIC Registers corresponds to this IRQ. */    nvic_reg = irq / 32;        /* Enable the Interrupt. */    NVIC_ICPR_REG( NVIC_BASE_PTR, nvic_reg ) = 1 << ( irq % 32 );    NVIC_ISER_REG( NVIC_BASE_PTR, nvic_reg ) = 1 << ( irq % 32 );          } /* ARM_CORTEX_M4__enable_interrupt() */

 Here is how I call it:

    /* Enable interrupts for Watchdog. */    ARM_CORTEX_M4__enable_interrupt( INT_Watchdog );

I was also unable to break during the interrupt. However, I did verify the interrupt was triggering by toggling a GPIO pin in the interrupt and then using my oscilloscope to verify that pin toggled. I"m unfamililar with the RFVBAT register. The GPIO trick may be something worth trying.

[mataylor]

Ignisuti,

I was hoping that this would resolve my issue as I was not enabling the interrupt vector, but unfortunately it has not. I must still be missing something. Does any one know if there are sequencing requirments for enabling the wdog ISR registers.

Currently I am performing the steps to enable the wdog & isr in the following sequence.

1) Install WDT isr with "_int_install_kernel_isr"

2) disable system interrupts "_int_disable"

3) unlock wdt

4) set prescaler timeout then STCTRLH registers

5) enable system interrupts "_int_enable"

6) enable ARM M4 WDT interrupt for IRQ 22 / Vecotor 38.

7) start periodic update task (which i disable to generate a time out for testing)

Thanks again for the suggestions.

[mataylor · Accepted solution]

All,

Thanks for you help. To get the WDT ISR configured correctly i used the _bsp_int_init(irq, prio, subprio, enable); macro for my BSP.

The steps to enable the IRQ correctly are shown below:

0) Configure BSP to place vector table in RAM by modifying user_config.h

#define MQX_ROM_VECTORS          0

0.5) modify project .icf file to place .vectors_ram in fast RAM

place at address mem:__region_VECTOR_TABLE_start__ { readwrite section .vectors_ram };

1) Install WDT isr with "_int_install_kernel_isr"

2) disable system interrupts "_int_disable"

3) unlock wdt

4) set prescaler timeout then STCTRLH registers

5) enable system interrupts "_int_enable"

6) _bsp_int_init(INT_Watchdog, 0, 0, TRUE); enable ARM M4 WDT interrupt for IRQ 22 / Vecotor 38 / priority 0

7) start periodic update task (which i disable to generate a time out for testing)