Kinetis K64F missing documentation?

[davenadler]

We're evaluating the K64F for a family of instrumentation products, but I'm having trouble finding all the required documentation. On the NXP web site, I find only two documents about this chip:
K64P144M120SF5RM.pdf: K64 Sub-Family Reference Manual, Rev. 2, January 2014
K64P144M120SF5.pdf: Kinetis K64F Sub-Family Data Sheet, Rev. 6, 08/2015

Questions:

1. In the reference manual, in many places it says "Refer to chip configuration details".
   Where are "chip configuration details"?
2. Reference manual page 934, PDBx_SC field descriptions, Trigger Input Source Select, says:
   "Refer to chip configuration details for the actual PDB input trigger connections."
   Where is the table defining the values and possible PDB input triggers?
3. Reference manual page 459, DMAMUX_CHCFGn field descriptions DMA Channel Source, says:
   "See your device's chip configuration details for information about the peripherals and their slot numbers."
   Where is the table defining allowed values and corresponding peripherals?
4. Reference manual section 21.5.2, To enable a source with periodic triggering, step 5 says:
   "Select the source to be routed to the DMA channel. Write to the corresponding
   CHCFG register" - This appears to be an error.
   For periodic triggering, the source must be set to an "always on" source, right?
5. Where is the table of application notes, with links to the notes and associated source code, for Kinetis processors?
   The last thing I find with google is a list without links last updated in 2012...

Without this information, it is very hard for your customers to make use of these parts...
Any help would be much appreciated.

Thanks!
Best Regards, Dave

[xiangjun_rong]

Hi,

Pls refer to chapter 3 chip configuration in K64P144M120SF5RM.pdf.

For PDB triggering source, pls refer to section 3.8.1.1.2 PDB Input Trigger Connections.

For DMA requestion source, pls refer to section 3.3.9.1 DMA MUX request sources

Hope it can help you

BR

XiangJun Rong

[davenadler]

Hello XiangJun Rong - We are still waiting for answers to 4,5, and 6 above? It has been almost one month?
Answers would be much appreciated!
Thanks, Best Regards, Dave

[xiangjun_rong]

Hi, Dave,

I am sorry for the delay. Regarding the GPIO toggling based on  DMA plus PIT, You have to use DMA channel0 if you use PIT0 to trigger, use DMA channel1 if you use PIT1. I attach the fig here.

For DGPIO configuration,   you have to set the PORTx_PCRy as GPIO function and set the IRQC bits as 3(DMA request on either edge.). For example, if you use PIT0,  you have to use DMA channel0. Set the source bits of DMAMUX_CHCFG0 as 49(PORTA), 50(PORTB), 51 (PORTC)..., configure PIT0 registers and DMA registers, it is okay.

BR

Xiangjun rong

[xiangjun_rong]

Hi,

Pls refer to an4419.pdf.

[davenadler]

Thanks! To save other customers trouble, please consider updating the manual adding links in the PDF to the mentioned chapter, or at a very minimum say "Refer to chip configuration details chapter above"... I was looking for a separate document (as have other customers asking this question on this forum).

Can you answer questions 4 and 5 above?
Also, another apparent documentation error:

6) In reference manual 21.4.1 DMA channels with periodic triggering capability: PIT 1 is shown connected to DMA trigger 0. In reality, PIT 0 is connected to DMA trigger 0, right? Here's the erroneous diagram (also repeated in the text)

Thanks,
Best Regards, Dave