Hi
I see - the Open Source version uses an old method that requires each crystal used to have a suitable divider value. This is however not critical when using the PLL and a simple modification is to change
#elif CRYSTAL_FREQUENCY == 24000000
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_1024); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)
to
#elif CRYSTAL_FREQUENCY >= 24000000
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_1024); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)
If the crystal doesn't start it is possible that you have some additional loading in the HW (such as capacitors or feedback resistor) The TEENSY 3.1 has no loading and so uses the setting
#define OSC_LOW_GAIN_MODE
This must however suit the HW and so this may need to be un-commented (to use high gain mode instead) in order to allow a 32MHz crystal to start.
Regards
Mark