Kinetis I2C Clock Divider in the KL25Z

[tomsparks]

I have a question about the I2C module's clock divider field I2C0_F while using Processor Expert.  I was able to successfully set the SCL clock rate to 100kHz by setting the internal frequency to 24MHz and my 0-2 divider bits to 111 and my 3-5 divider bits to 011.  I understand that by selecting my internal frequency I'm actually setting the mul bits (bits 6-7), and that since my bus frequency is 24MHz the mul bits were set to 00 by processor expert to yield a mul divider value of 1.

What is puzzling me is the 0-2 divider bits and the 3-5 divider bits.  The overall divider value needed to be 240 to bring the 24MHz down to 100kHz.  I set them where I thought they might need to go, but that didn't seem to work.  I couldn't figure out the logic of these bits so I simply began randomly setting and clearing bits until I got the SCL frequency set to 100kHz.

I've read Freescale's AN4342 and on page 4 of that document they give an example of three different ways to achieve the same SCL frequency using three different values.  I can follow it until the 0-2 and 3-5 divider values need to be beyond the range possible with just six bits.  Are these bits some kind of offset from their normal placement, or are these bits multiples of one another with an offset?  Am I making this too complicated?

I should just move on knowing I have the proper values set to make things work, but this is really bugging me.  Can anyone explain how these bits work?

Thanks,

Tom

[adriancano · Accepted solution]

Hi Tom,

Yes I think this is kind of confusing because it does not say what you are configuring with that values. I will try to give you an explanation hoping this be more clear.

Referring to the reference manual in the section 38.3.2 I2C Frequency Divider register (I2Cx_F) we see that the register I2Cx_F has two fields:

-MULT --> This one configures the divider factor of the Bus clock. Leaving this MULT = 00 the Internal frequency = Bus Clock.

-ICR --> This value indicates the value of the SCL divider. The bits 0-2 and 3-5 correspond to the low and high part of the ICR register. You can check the SCL values corresponding to the ICR value in the Section 38.4.1.10 I2C divider and hold values.

The equation to determinate the I2C baud rate (SCL frequency in Processor Expert) is:

I2C baud rate = bus speed (Hz)/(mul × SCL divider)

Here is an example to apply the equation:

bus speed (Hz) = 24 MHz = 24 000 000 Hz

mul = 0 (in this case this when we set Internal frequency = Bus Clock in the Internal frequency (multiplier factor) in Processor Expert)

SCL divider = 240 (Check the table 38.41 The ICR we set in PEx is 0-2 = 111  3-5 = 011 this ICR= 011111 = 0x1F)

Applying the values in the equation:

24 000 000 / (1 * 240) = 100 000 Hz = 100 KHz

I hope this information can help you.

Regards,

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[tomsparks]

Thank you Adrian!  I had that chapter on my desk when I wrote this question.  I just needed to read it a bit more carefully.  What's confusing, (without the benefit of Table 38-41) is that it seems the bits should be numerically related to the divider value, but instead they are simply indexes for a items on a list.

The bottom line is I needed to read the manual a lot closer.

Thanks again,

Tom