Kinetis DDR configuration of DDR_PAD_CTRL register - missing documentation

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Kinetis DDR configuration of DDR_PAD_CTRL register - missing documentation

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moliveira
Contributor I

I'm trying to configure the DDR interface in a Kinetis K61 but I'm struggling with the correct settings for the DDR_PAD_CTRL register.

How should one chose correct settings for the SPARE_DLY_CTRL bits? The documentation (reference manual K61P256M150SF3RM rev 2) doesn't explain how the buffers correlate with the behavior of the DDR PHY.

What is delay chain #0?

What is spare logic?

What are buffers?

It is also confusing to see that the reset value for the reserved bits [8:15] are set to 0x2 when the documentation says "This read-only field is reserved and always has the value zero." This is obviously not the case as I can read a value != 0 after reset.

All in all this register lacks documentation needed to understand how it should be used.

Our setup is in all aspects identical with the TWR-K70F120M board and in the code examples we can find the SPARE_DLY_CTRL is configured to "10 buffers", why is that?

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bjoernjohanness
Contributor III

I'd appreciate if Freescale would reply to the questions. It bothers me a lot that the example code writes to supposedly reserved bits: "This read-only field is reserved and always has the value zero."

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

Kinetis K70 is using same DRAM controller IP of ColdFire MCF54418, and I checked MCF54418 reference manual about DDR I/O Pad Control Register (DDR_PADCR) register with below description:

DDR_PAD_CTL_1.png

DDR_PAD_CTL_2.png

That could interpret the K70 DDR2 initialization code of DDR_PAD_CTRL register value:

DDR_PAD_CTRL = 0x01030203; 

MCF54418 reference manual could be downloaded from below link:

http://cache.freescale.com/files/32bit/doc/ref_manual/MCF54418RM.pdf


Wish it helps.
best regards
Ma Hui

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Treskewl
Contributor II

Hi,

I'm currently developing with a K70, but soon to migrate to a K61 when our next prototypes come through (I believe these processors are fundamentally the same, with the exception of a graphics LCD support).

My questions relates to the DDR configuration, in which I'm trying to use the K70 DDR configuration tool:

1. You stated in a previous post:

Kinetis K70 is using same DRAM controller IP of ColdFire MCF54418

However, I find that the descriptions for PAD_ODT_CS0 is different for the K70. Can you please explain which one is correct?

     pastedImage_0.png

2. In trying to use the K70 DDR configuration tool, I cannot seem to determine how the parameter io_odt translates to a value in the DDR_PAD_CTRL register in the generated code. I've played around with different values. I originally thought it may just be in Ohm units. So I tried 0, 50, 75, and 150. All but 75 return bits 24-25 in DDR_PAD_CTRL as 0, where having io_odt = 75, returns bits 24-25 as 1. This doesn't match the specification detailed in the reference manual (shown above). I also tried values io_odt from 0 to 3, assuming that the tool might just mask the value and slot it in the appropriate fields in the DDR_PAD_CTRL register, but again, they all returned 0 in bit 24-25.

3. In trying to use the K70 DDR configuration tool, I configure casLatency = 3. But the K70 DDR configuration tool generates a 7 in bits 0 to 3 of DDR_CR03, implying a latency linear of 3.5 cycles, I was expecting to see 6 in those bits. Have I misunderstood something?

Thanks in advance.

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bjoernjohanness
Contributor III

Thanks for your reply Ma, it's very appreciated!

Looks like you're right about that particular register and that it is the same as for MCF54418. It does explain DDR_PAD_CTRL = 0x01030203;

I have a few follow up questions:

  1. Short term this is an answer but really, is this how we are supposed to configure our processor: Find another uC RM and "hope" that it is the same? I don't feel good about this approach!
  2. The two uC's only share the DDR_PAD_CTRL and DDR_RCR. All other (DDR_CRxx), are different. How should I interpret that?
  3. The OFFSET_VALUE doesn't seem to apply to the K61 since it doesn't use differential DQS?
  4. Possibly, we've figured out the definition of DDR_CTRL_PAD. What about all the other registers mentioned in this thread?

Basically, why is it so hard for Freescale to supply my with the a complete and detailed description of the DRAM controller? It is mighty hard to troubleshoot in the dark, please help!

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perlam_i_au
Senior Contributor I

In this case you can use the Kinetis K70 DDR memory initialization tool, on all the examples field SPARE_DLY_CTRL with 0x3 (10 buffers), I am still looking for information regard chain #0, spare logic and buffers. :S


Have a nice day,
Perla Moncada

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moliveira
Contributor I

I wasn't aware of the tool so I tried it but the results where not very convincing:

First of all the MT47H64M16.mem file used for theTWR-K70F120M board has an error:

rowAddr = 14 should be rowAddr = 13

rowAddr = 14 causes the DDR controller to configure a 256Mbyte memory when the memory is only 128Mbytes.

Then there is settings for clkendly and cmddly which both are set to zero. The comment in the memory configuration file states:

"clkendly, if 0, 1 will be provided"

"cmddly, if 0, 2 will be provided"

Both setting should have impact on the DDR_CR57 register but the resulting c-file shows:

DDR_CR57 = 0x01000000;    // odtalten

Coming back to the DDR_PAD_CTRL register, yes the SPARE_DLY_CTRL is configured to 10 buffers but the tool generates this code:

DDR_PAD_CTRL = 0x01030203;

According to the RM (K61P256M150SF3RM) bit 16-17 are reserved and so are bit 9, why does the tool set these values??? (Bit 9 should be cleared according to the manual)

What shall I as a developer trust, the tool or the documentation?

Or should I look at Freescale code...

If I take the MQX 4.1 BSP for a reference:

Function _bsp_ddr2_setup() in init_hw.c

Examples:
code: * (vuint_32 *)(0x400Ae1ac) = 0x01030203;
manual: DDR_PAD_CTRL - bits 4-23 are reserved: 'This read-only field is reserved and always has the value zero.'

code: ddr->CR06 = 0x02904002;
manual: DDR_CR06 - bit 25 is reserved: 'This read-only field is reserved and always has the value zero. Must be cleared.'

code: ddr->CR23 = 0x00040302;
manual: DDR_CR23 - bits 0-31 are reserved: 'This read-only field is reserved and always has the value zero.'

code: ddr->CR28 = 0x00000003;
manual: DDR_CR28 - bit 1 is reserved: 'This read-only field is reserved and always has the value zero. Must be cleared.'

code: ddr->CR34 = 0x02020101;
manual: DDR_CR34 - bits 16-31 are reserved: 'This read-only field is reserved and always has the value zero. Must be cleared.'

code: ddr->CR36 = 0x01010201;
manual: DDR_CR36 - bits 0-31 are reserved: 'This read-only field is reserved and always has the value zero.'

It's all very frustrating and it consumes a lot of time. The RM is still in Preliminary status (as it has been the last 2,5 years). I would appreciate some guidance.

Regards Mikael