Hi, Divide,
I am not very clear about your question.
Generally, the PWM cycle time of SM0/SM1/SM2/SM3 is controlled by the PWMA_SM0VAL1 - PWMA_SM0INIT if you use Master Sync of SM0 to synchronize all the SM1/SM2/SM3 modules. In the case, if you enable the Fractional Delay Logic function, obviously, setting the PWMA_SM0FRACVAL1 register to non-zero value is sure to take effect on the PWM cycle time. But if you use EXT_SYNC signal to synchronize the SM0/SM1/SM2/SM3, I think the external signal will control the PWMA cycle time.
I do not know why you use EXT_SYNC signal to synchronize all PWM sub-modules, if possible, I suggest you use Master Sync of SM0 to synchronize all the SM1/SM2/SM3 modules, and set the PWMA_SM0FRACVAL1 register to zero, in the scenario, the PWMA cycle time is only determined by PWMA_SM0VAL1 - PWMA_SM0INIT, the disadvantage is that the PWMA_X0 signal is restricted, because PWMA_SM0VAL1 is used to control both the PWMA cycle time and falling edge of PWMA_X0 signal.
Hope it can help you
BR
XiangJun Rong