KV31F DSPI Master(SPI0) is not receiving data from DSPI Slave(SPI1)

[SANGEERTH-P]

Hello all,

I am using FRDM-KV31F512VLL Board. There are 2 DSPI instances available in this board. What I am trying to do is configure one DSPI as Master and the other DSPI as Slave. And I was trying to send a set of data from the master to the slave. And send an other different set of data from the slave to the master. What i see from my code is Master is able to send and receive data to and from the slave. But the slave is able to just send data to the Master and the Slave is not able to receive the data. I have configured the slave in Interrupt mode and master in Polling mode.

 I was sending data=[1,2,3,4,5,6] from the Slave to the Master.

And the master was able to receive this data. 

I was sending data=[7,8,9,A,B,C] from the Master to the Slave.

The Slave was not able to receive more that first two data.

When I set breakpoints in my code, what I see is after this data '8' gets POPED UP from the FIFO Register, is some RFOF-Receive FIFO Overflow Flag getting set up. I really don't understand the point how is this getting set up.

This is the piece of code which i made for master send.

This is the piece of code which i used for slave receive.

Please help me to make this transfer successful. 

[myke_predko]

@SANGEERTH-P 

This is going to sound funny for people who have seen my previous posts, but could you post your code?  Ideally limit it to the transfers.  

On other Kinetis SPI implementations, the RX FIFO buffer is 4 entries (and entry being a data block from 4 to 16 bits long) and I find it suspiciouis that you're having problems after 8 byte transfers.  

In your first transfers (from Slave to Master) how are you reading the data?  How do you know you're clearing the Master's RX FIFO when each byte comes in?  Are you monitoring the return values from the API calls?  I wonder if more information is being produced than what you are looking at.  

I suspect that in using polling mode for the master you're not always clearing the master's RX FIFO.  

myke

[SANGEERTH-P]

Hi Sir

I have herewith attached the code.

The Master RxFIFO is getting drained sir and I checked it by keeping breakpoints. It is working fine. And even for Slave RxFIFO is getting drained but one over flow flag RFOF is being set always. That is the only reason I see that the transfer is not happening. Please help me resolve this issue.

[myke_predko]

Hi @SANGEERTH-P 

What is the source file should I be looking at?  There's "spi1.c", "spi2.c" & "spi4.c" and all of them have a "main" method in them.  It looks like you've put three experiements' source code into the same project and I'm not sure what is the most current/the one your referencing the question to.  

Regardless, I don't see any checks of the results of the (D)SPI APIs.  I would suggest that you put in a check like:

 if (kStatus_Success != (status = DSPI_MasterTransferEDMA(OLED_DSPI_MASTER_BASEADDR
                                                        , &oledDSPIEDMAMasterHandle
                                                        , &actualOLEDSPIXfer))) {
    PRINTF("\nOLEDDSPI_MasterHalfTransferEDMA Error: %i"
         , status);
    for (;;) {  }
  }

In all your API calls.  I suspect there's information in the return codes that would be of value to you.  

myke

[SANGEERTH-P · Accepted solution]

Thank you so much for your reply sir. The working file is spi2.c. However, I found answer in one of your other posts sir where in you have given a git repository link 

Now I changed the DSPI code completely and also added this EDMA part and this was perfectly working.

Thank you so much for your kind help sir. The slave was able to send and receive data from the master perfectly as expected and the master was also able to send as well as receive the data from the slave.