KV10z32VL7 is automatically reseted despite that the watchdogt timer is disabled

[amerzater]

I have a design of customized board for control board based on KV10Z32VL7 .the signal on the reset pin is shown at the graph below.

the watchdog timer is disabled. 

what could be the problem?

[amerzater]

I realized that the problem was in NMI_b , in my design I am using it as an output connected to an optocoupler . it seems that the opto was pulling down the NMI_b during the startup. when I removed the connection between that Pin and the opto , it simply worked.

now, any idea how to use NMI_b as an output without affecting the startup procedure?

[Hui_Ma]

Hi,

You can add an external 4.7Kohm pull up resistor with /NMI_b pin.

Wish it helps.

Have a great day,
Mike

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[mjbcswitzerland]

Hi

You can disable the NMI pin in the flash configuration.

Regards

Mark

[mjbcswitzerland]

Hi

This is typical of a chip that:
1- has no code loaded to it, or
2- has code loaded that immediately crashes, or
3- has code disabling the watchdog too late (after 256 clock cycle limit)

Regards

Mark

[amerzater]

Many Thanks Mr. Mark

I am using MCUXpresso IDE with SDK 2.0 MKV10Z32xxx7 . and I am using USBDM programmer to load the program to the chip.

even by loading the SDK GPIO example to the chip (after reconfiguring the pins MUX and the clock to use internal clock ) ,  I am still having the same problem..

can you please help?

[amerzater]

resetISR routine is showen at the image below.which clears that WDG is disabled right after the reset.

[Hui_Ma]

Hi,

The code below SystemInit() is gray, which doesn't included during compile.

The SystemInit() function provided disable Watchdog function with default DISABLE_WDOG definition.

From you description,  could you check if you can debug into main() function?

If not, which code will cause the chip reset?

Have a great day,
Mike

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[amerzater]

Many Thanks, Mr. Mark

actually, I have DISABLE_WDOG defined as 1 already..

but running any example code is causing the chip to reset it self..

I have tried two different chips on two different board of the same customized design and I got the same result.

[amerzater]

actually, I am not providing any clock signal to the WDOG module (InActive)