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KM34Z128 uart config for 300bd 7E1

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KM34Z128 uart config for 300bd 7E1

‎06-04-2019 03:10 AM
3,282 Views
raja_m
Contributor I

I used KM34Z128.  it is working 300 bd and 8N1. but not able configure  7E1 mode. how to configure 300bd 7E1

UART3_Init(UART_MODULE_INTRMODE_CONFIG1(SET_300_BR,SystemState.SysClk));
UART_InstallCallbackUART2_UART3(UART_INTERRUPT_PRIORITY, OpticalEventHandler);

#define UART_MODULE_INTRMODE_CONFIG(brate,bclk) \
(tUART){ \
/* BDH */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,bclk)>>8)&0x1f), \
/* BDL */ ((CALC_SBR(brate,bclk)>>0)&0xff), \
/* C1 */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)| \
/* .. */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)| \
/* .. */ CLR(UART_C1_ILT_MASK)|CLR(UART_C1_PE_MASK)| \
/* .. */ CLR(UART_C1_PT_MASK), \
/* C2 */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)| \
/* .. */ SET(UART_C2_RIE_MASK)|CLR(UART_C2_ILIE_MASK)| \
/* .. */ SET(UART_C2_TE_MASK)|SET(UART_C2_RE_MASK)| \
/* .. */ CLR(UART_C2_RWU_MASK)|CLR(UART_C2_SBK_MASK), \
/* S2 */ CLR(UART_S2_RXEDGIF_MASK)|CLR(UART_S2_MSBF_MASK)| \
/* .. */ CLR(UART_S2_RXINV_MASK)|CLR(UART_S2_RWUID_MASK)| \
/* .. */ CLR(UART_S2_BRK13_MASK), \
/* C3 */ CLR(UART_C3_T8_MASK)|CLR(UART_C3_TXDIR_MASK)| \
/* .. */ CLR(UART_C3_TXINV_MASK)|CLR(UART_C3_ORIE_MASK)| \
/* .. */ CLR(UART_C3_NEIE_MASK)|CLR(UART_C3_FEIE_MASK)| \
/* .. */ CLR(UART_C3_PEIE_MASK), \
/* MA1 */ SET(UART_MA1_MA(0x00)), \
/* MA2 */ SET(UART_MA2_MA(0x00)), \
/* C4 */ CLR(UART_C4_MAEN1_MASK)|CLR(UART_C4_MAEN2_MASK)| \
/* .. */ CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,bclk)>>0)&0x1f), \
/* C5 */ CLR(UART_C5_TDMAS_MASK)|CLR(UART_C5_RDMAS_MASK), \
/* C7816 */ CLR(UART_C7816_ONACK_MASK)|CLR(UART_C7816_ANACK_MASK)| \
/* ..... */ CLR(UART_C7816_INIT_MASK)|CLR(UART_C7816_TTYPE_MASK)| \
/* ..... */ CLR(UART_C7816_ISO_7816E_MASK), \
/* IE7816 */ CLR(UART_IE7816_WTE_MASK)|CLR(UART_IE7816_CWTE_MASK)| \
/* ...... */ CLR(UART_IE7816_BWTE_MASK)|CLR(UART_IE7816_INITDE_MASK)| \
/* ...... */ CLR(UART_IE7816_GTVE_MASK)|CLR(UART_IE7816_TXTE_MASK)| \
/* ...... */ CLR(UART_IE7816_RXTE_MASK), \
/* IS7816 */ CLR(UART_IS7816_WT_MASK)|CLR(UART_IS7816_CWT_MASK)| \
/* ...... */ CLR(UART_IS7816_BWT_MASK)|CLR(UART_IS7816_INITD_MASK)| \
/* ...... */ CLR(UART_IS7816_GTV_MASK)|CLR(UART_IS7816_TXT_MASK)| \
/* ...... */ CLR(UART_IS7816_RXT_MASK), \
/* WP7816T0 */ SET(UART_WP7816_T_TYPE0_WI(0x0a)), \
/* WP7816T1 */ SET(UART_WP7816_T_TYPE1_CWI(0x00))| \
/* ........ */ SET(UART_WP7816_T_TYPE1_BWI(0x0a)), \
/* WN7816 */ SET(UART_WN7816_GTN(0x00)), \
/* WF7816 */ SET(UART_WF7816_GTFD(0x00)), \
/* ET7816 */ SET(UART_ET7816_TXTHRESHOLD(0x00))| \
/* ...... */ SET(UART_ET7816_RXTHRESHOLD(0x00)), \
/* TL7816 */ SET(UART_TL7816_TLEN(0x00)) \
}

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‎06-05-2019 01:31 PM
3,010 Views
FelipeGarcia
NXP Employee
NXP Employee

Hi Raja M,

 

Please check snippet below. 7 bit data is not supported, you can only set 8 or 9 bit data by setting M bit in the UART_C1 register.

 pastedImage_2.png

Have a great day,
Felipe

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‎06-05-2019 09:46 PM
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raja_m
Contributor I

Hi Felipe García

 May it will support (7E1)7 bit data,1parity and 1stop bit

UART_C1 register -  if  i enable SET(UART_C1_PE_MASK) ,7E1 should work but for me not working why? any other configuration need?

 

pastedImage_2.png

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‎06-07-2019 09:59 AM
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FelipeGarcia
NXP Employee
NXP Employee

Hi Raja,

 

By checking your code above I see you are not setting Parity Enable bit in the in the UART configuration.

 

Could you please try as below?

 

#define UART_MODULE_INTRMODE_CONFIG(brate,bclk) \

(tUART){ \

/* BDH */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,bclk)>>8)&0x1f), \

/* BDL */ ((CALC_SBR(brate,bclk)>>0)&0xff), \

/* C1 */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)| \

/* .. */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)| \

/* .. */ CLR(UART_C1_ILT_MASK)|SET(UART_C1_PE_MASK)| \

/* .. */ CLR(UART_C1_PT_MASK), \

/* C2 */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)| \ ...

...

Hope it helps!

 

Best regards,

Felipe

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- We are following threads for 7 weeks after the last post, later replies are ignored
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‎06-09-2019 09:19 PM
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raja_m
Contributor I

Hi Felipe García

 SET(UART_C1_PE_MASK)

 you this options checked please let me any other option

void OpticalEventHandler(UART_CALLBACK_SRC module, UART_CALLBACK_TYPE type, int8 status)
{
vuint8 ucRxData,temp;

if(type==RX_CALLBACK)
{
if(OPTICAL_RXDATAREG_FLAG())
{
Optical_Rx_timeout = 0;
//OPTICAL_CLEAR_RXFUL_FLAG;
ucRxData = OPTICAL_DATA_REGISTER();

if (OpticalPacketReceptionInProgress == 1)
{
Optical_RX_cnt+=1;
OPTICAL_RX_BUF[Optical_RX_cnt] = ucRxData;
}
#if DLMSHDLC_ENABLE == ENABLE
else if((ucRxData == 0x7E)||(ucRxData == '/') )
#else
else if((ucRxData == FRAME_HEADER_START) || (ucRxData == START_CHAR) || (ucRxData == 0x00)||(ucRxData == 0x01))
#endif
{
Optical_RX_cnt = 0;
OPTICAL_RX_BUF[Optical_RX_cnt] = ucRxData;
OpticalPacketReceptionInProgress = 1;
}
}
}

else if(type==TX_CALLBACK)
{
if(Optical_TX_cnt >= Optical_TX_len)
{
OPTICAL_DISABLE_TXINT();
//OPTICAL_ENABLE_RXINT();
OpticalPacketTxInProgress = 0;
Optical_TX_cnt = 0;
#if (ADE7878_MODBUS == ACTIVE)
RTUTx_flag =0;
#endif
return;
}
UART3_D = OPTICAL_TX_BUF[Optical_TX_cnt];
Optical_Tx_timeout = 0;
Optical_TX_cnt+=1;

}
}

#define UART_MODULE_INTRMODE_CONFIG(brate,bclk)                               \
(tUART){                                                                      \
/* BDH      */ CLR(UART_BDH_RXEDGIE_MASK)|((CALC_SBR(brate,bclk)>>8)&0x1f),   \
/* BDL      */ ((CALC_SBR(brate,bclk)>>0)&0xff),                              \
/* C1       */ CLR(UART_C1_LOOPS_MASK)|CLR(UART_C1_RSRC_MASK)|                \
/* ..       */ CLR(UART_C1_M_MASK)|CLR(UART_C1_WAKE_MASK)|                    \
/* ..       */ CLR(UART_C1_ILT_MASK)|SET(UART_C1_PE_MASK)|                    \
/* ..       */ CLR(UART_C1_PT_MASK),                                          \
/* C2       */ CLR(UART_C2_TIE_MASK)|CLR(UART_C2_TCIE_MASK)|                  \
/* ..       */ SET(UART_C2_RIE_MASK)|CLR(UART_C2_ILIE_MASK)|                  \
/* ..       */ SET(UART_C2_TE_MASK)|SET(UART_C2_RE_MASK)|                     \
/* ..       */ CLR(UART_C2_RWU_MASK)|CLR(UART_C2_SBK_MASK),                   \
/* S2       */ CLR(UART_S2_RXEDGIF_MASK)|CLR(UART_S2_MSBF_MASK)|              \
/* ..       */ CLR(UART_S2_RXINV_MASK)|CLR(UART_S2_RWUID_MASK)|               \
/* ..       */ CLR(UART_S2_BRK13_MASK),                                       \
/* C3       */ CLR(UART_C3_T8_MASK)|CLR(UART_C3_TXDIR_MASK)|                  \
/* ..       */ CLR(UART_C3_TXINV_MASK)|CLR(UART_C3_ORIE_MASK)|                \
/* ..       */ CLR(UART_C3_NEIE_MASK)|CLR(UART_C3_FEIE_MASK)|                 \
/* ..       */ CLR(UART_C3_PEIE_MASK),                                        \
/* MA1      */ SET(UART_MA1_MA(0x00)),                                        \
/* MA2      */ SET(UART_MA2_MA(0x00)),                                        \
/* C4       */ CLR(UART_C4_MAEN1_MASK)|CLR(UART_C4_MAEN2_MASK)|               \
/* ..       */ CLR(UART_C4_M10_MASK)|((CALC_BRFA(brate,bclk)>>0)&0x1f),       \
/* C5       */ CLR(UART_C5_TDMAS_MASK)|CLR(UART_C5_RDMAS_MASK),               \
/* C7816    */ CLR(UART_C7816_ONACK_MASK)|CLR(UART_C7816_ANACK_MASK)|         \
/* .....    */ CLR(UART_C7816_INIT_MASK)|CLR(UART_C7816_TTYPE_MASK)|          \
/* .....    */ CLR(UART_C7816_ISO_7816E_MASK),                                \
/* IE7816   */ CLR(UART_IE7816_WTE_MASK)|CLR(UART_IE7816_CWTE_MASK)|          \
/* ......   */ CLR(UART_IE7816_BWTE_MASK)|CLR(UART_IE7816_INITDE_MASK)|       \
/* ......   */ CLR(UART_IE7816_GTVE_MASK)|CLR(UART_IE7816_TXTE_MASK)|         \
/* ......   */ CLR(UART_IE7816_RXTE_MASK),                                    \
/* IS7816   */ CLR(UART_IS7816_WT_MASK)|CLR(UART_IS7816_CWT_MASK)|            \
/* ......   */ CLR(UART_IS7816_BWT_MASK)|CLR(UART_IS7816_INITD_MASK)|         \
/* ......   */ CLR(UART_IS7816_GTV_MASK)|CLR(UART_IS7816_TXT_MASK)|           \
/* ......   */ CLR(UART_IS7816_RXT_MASK),                                     \
/* WP7816T0 */ SET(UART_WP7816_T_TYPE0_WI(0x0a)),                             \
/* WP7816T1 */ SET(UART_WP7816_T_TYPE1_CWI(0x00))|                            \
/* ........ */ SET(UART_WP7816_T_TYPE1_BWI(0x0a)),                            \
/* WN7816   */ SET(UART_WN7816_GTN(0x00)),                                    \
/* WF7816   */ SET(UART_WF7816_GTFD(0x00)),                                   \
/* ET7816   */ SET(UART_ET7816_TXTHRESHOLD(0x00))|                            \
/* ......   */ SET(UART_ET7816_RXTHRESHOLD(0x00)),                            \
/* TL7816   */ SET(UART_TL7816_TLEN(0x00))                                    \
}

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‎06-10-2019 09:35 AM
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FelipeGarcia
NXP Employee
NXP Employee

Hi Raja M,

 

Could you please try one of our examples and modify the SET(UART_C1_PE_MASK) register?

 

You can find the examples in the following link:

https://www.nxp.com/downloads/en/lab-test-software/TWR-KM34_DEMO_SW.zip

 

Are you configuring the terminal to receive the parity correctly?

 

Please let me know your findings.

 

Best regards,

Felipe

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‎06-13-2019 09:54 PM
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raja_m
Contributor I

Hi Felipe García,

           modified  the SET(UART_C1_PE_MASK)  but   it is not working. Please give me valuable support. 
 

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‎06-17-2019 10:43 AM
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FelipeGarcia
NXP Employee
NXP Employee

Hi Raja M,

 

Please accept my apologies for the late reply. I did the following testing to work with 7 bits data and odd parity and it worked well.

 

I am using TWR-KM34Z50MMV3 board (KM34Z128 MCU same as yours) and I used the uartisr_test example you can download from https://www.nxp.com/downloads/en/lab-test-software/TWR-KM34_DEMO_SW.zip

 

I modified this example by configuring UART_C1[PE] | UART_C1[PT]. This were the only changes I made, please see attached the modified header file.

 

I configured the serial term as follows:

pastedImage_2.png

Using this I got the following behavior:

pastedImage_4.png

 

As you can see TX and RX worked correctly with 7 bits data and odd parity.

 

I hope this helps you.

 

Best regards,

Felipe

uart.h.zip
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‎06-09-2019 08:30 AM
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raja_m
Contributor I

Dear Felipe García

This option enable and checked please let me know any other option

Thanks and Regards

Raja M

Dept : product and Development

Direct: 91 0471 2477510 | Cell: +91 9790896978

raja_m@cms.co.in | Web: www.cms.co.in

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