KL82Z Manual MCG Block Diagram Confusion

[daviddyao]

Hi, I'm a bit confused at the MCG block diagram for the KL82Z and I think there's a mistake.

Looking at KL82P121M72SF0RM, Figure 29-1, the PLL subsection of the MCG block diagram doesn't match the calculation of MCGPLL0CLK and MCGPLL0CLK2X described in step 3b of 29.6.3.1 Example 1. Specifically, the way the diagram is drawn makes it look like the PLL will inherently multiply by 2 before the effects of VDIV because VCOOUT is taken from AFTER the /2 block. I think it should looks something like the following:

I used a similar diagrams in this article for reference:

Tamper Protection Secures MCU-Based System IP | DigiKey 

Thanks.

[xiangjun_rong]

Hi, David,

I aggree with you, I do not think the description in step 3b of 29.6.3.1 Example 1 is correct.

With 16MHz external clock source(or crystal), set the C1[PRDIV] value of
2'b001, the PLL reference divider is 2 , the PLL input clock frequency will be 16MHz/2=8mHz.

With the C6[VDIV] set to 5'b01110, or multiply-by-30, the VCO output clock frequency will be

8MHz*30*2=480Mhz instead of 240mhz.

In the case, I will confirm if there is the /2 intrinsic divider.

BR

Xiangjun Rong

[xiangjun_rong]

Hi,

I think your above diagram is correct, the /2 divider is not included in the feedback loop.

BR

XiangJun Rong