Hi Briceag,
Please download the SDK_2.0_FRDM-KL46Z from this web.
You can refer the lptmr project.
This demo toggle LED in LPTMR interrupt every one second.
Best Regards,
Robin
Hi
This is code to initialise to run a KL46 at 48MHz (24MHz bus and flash) from an 8MHz crystal [the hex values are noted in brackets for simple comparison]:
MCG_C2 = (MCG_C2_RANGE_1M_8M | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // select crystal oscillator and select a suitable range [0x9c or 0x94 depending on HW]
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_256); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used) [0x98]
while ((MCG_S & MCG_S_OSCINIT) == 0) {} // loop until the crystal source has been selected
while ((MCG_S & MCG_S_IREFST) != 0) {} // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes [0x23]
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS); // set the PLL multiplication factor [0x58]
while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {} // loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides [0x10010000]
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selected
This is verified by the uTasker KL46 simulator below.
Further details:
http://www.utasker.com/kinetis/MCG.html
References:
http://www.utasker.com/kinetis/FRDM-KL46Z.html
http://www.utasker.com/kinetis/TWR-KL46Z48M.html
These is the user setup to achieve this in the uTasker project:
#define CRYSTAL_FREQUENCY 8000000 // 8 MHz crystal
#define CLOCK_MUL 48 // the PLL multiplication factor to achieve MCGPLLCLK operating frequency of 98MHz (x24 to x55 possible) (MCGPLLCLK/2 is 48MHz - required by USB)
#define SYSTEM_CLOCK_DIVIDE 2 // divide (1,2,3..16 possible) to get core clock of 48MHz
#define FLASH_CLOCK_DIVIDE 2 // divide from core clock for bus and flash clock (1,2,3..8 possible) 24MHz
#define OSC_LOW_GAIN_MODE // oscillator without feedback resistor or load capacitors so use low gain mode (this is removed when the crystal is loaded)
Note the option that is HW dependent!!!
Regards
Mark
Kinetis for professionals: http://www.utasker.com/kinetis.html
Hi,
Unfortunately it doesn't work. I did the same thing as you said.
#define CLKSTS_MASK 0x08
#define CLKST_MASK 0x0C
void BootClockRUN()
{
MCG_C2 = 0x94;
MCG_C1 = 0x98;
while((MCG_S & (1<<1)) == 0){}
while((MCG_S & (1<<4)) !=0){}
while((MCG_S & CLKSTS_MASK) != CLKSTS_MASK){}
MCG_C5 = 0x23;
MCG_C6 = 0x58;
while((MCG_S & (1<<5)) ==0){}
while((MCG_S & (1<<6)) ==0){}
SIM_CLKDIV1 = 0x10010000;
while(((MCG_S & CLKST_MASK)) != CLKST_MASK){}
}This is the board I have:
Any other idea ?
Thank you,
