KL33 GPIO - slow fall time input signal - potential damage to MCU query?

[paulschoenke]

Hello – our customer has a technical question regarding the digital input for the Kinetis KL33 part. They have a circuit where the output has a 500ms fall time (3.0V to 0.7V) that is connected to the digital input of the processor. They only check the high and low level and timing is not critical.  Essentially it’s an input from an external source that gets monitored regularly. 

The datasheet clearly shows that there is VIL and VIH limit, however, it doesn't indicate that these inputs are Schmitt trigger inputs. Table 5, page 7 http://www.nxp.com/assets/documents/data/en/data-sheets/KL33P80M48SF3.pdf

The main question is, will this fall time cause any damage to the digital input of the microcontroller in the long run. During the500ms fall-time the digital input will see a voltage that is in-between the VIL and VIH - this is our main concern.

From what I can tell, it doesn’t look like there is an issue with the voltage fall or rise time at 500ms.  There is 0.198V of hysteresis by the upper and lower limits, but they are safe enough away from the VIH, VIL, to not have any concern.

It appears to me that the limits that are being referenced to in the datasheet are the limits that are required to produce a digital high (0.75 x 3.3V = 2.475V) and a digital low (0.35 x 3.3V = 1.155V).  If there is voltage between these ranges, then NXP cannot guarantee a high or low to be read on the GPIO.  Is that correct?

However, my customer still has the concern of potential long-term damage to the MCU due to the conditions of this input on the I/O pin.

Can you please verify if this will or will not have any long term implications that could cause damage to the MCU?

Any feedback or input is welcomed and appreciated!

Thanks again!

Paul

[Robin_Shen]

Hi Paul,

Please see below simplified I/O block diagram.

It has an schmitt trigger when enbale input and input hysteresis voltage is minmum 0.06Vdd, and don't trigger internal circuit frequently, and I think it don't damage the MCU when input voltage in the middle range.

Best Regards,

Robin

[paulschoenke]

I should have also mentioned that it looks like internally the part has a 47kohm pulldown resistor.  currently the software samples this GPIO every 100ms or so, but this could be adjusted to be 100ms or another frequency or time frame if that would alleviate potential damage to the MCU.  this is a common circuit and interface on several projects so my customer really needs verification on this as soon as possible as they're trying to release this to production and want to know if there is anything that should be changed prior to release.

Thanks again!

[egoodii]

The datasheet-table you reference does give a Vhys of 0.06xVdd, so I would expect NO errant behavior, and certainly no damage, from a 'slow edge' -- just a slight increase in power while the input voltage is in the mid-range.  Granted, as you say you won't be able to GUARANTEE a sampled switching-point-voltage on that ramp until it hits the rated Vil or Vih, but you can 'generally expect' to switch very near 1/2-rail.

There should only be a 47K (20K to 50K) pull-down on the pin if you've expressly enabled it.