Hi Chris
WIth 48MHz system clock, 24MHz bus clock and 24MHz flash clock (last one probably not relevant) the port output toggle rate using the normal GPIO is 8MHz
The same using the FGPIO is 24MHz.
The FPGIO accesses are 3x faster (1 output change per core clock, compared to 1 output change per 3 core clocks).
As Earl pointed out, it depends on your test SW since if it has additional instructions being executed the port accesses will only be a percentage of the overhead.
Regards
Mark
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