KL03: ADHSC=1 increases VLPS current from 2 uA to 85 uA

[martinkrause]

We have a KL03 board doing ADC measurements with internal ADCLK when the CPU is running. If nothing is to do we enter VLPS mode. Until now in VLPS mode we measured a MCU current of 2 uA. Now I set ADHSC bit to 1 to use the highest possible ADCLK. And surprisingly this increasese the current measured in VLPS from 2 uA to 85 uA??

Where does this heavy current increase come from? We do single ADC conversions, so the ADC (and thus the ADCLK) should be not running during VLPS (during VLPS we do not use/need ADC measurements). But if the ADCLK is not running during VLPS why is the MCU current increased if I set ADHSC to 1? If I configure ADHSC to 0 before entering VLPS, the current is 2 uA. So a possible workaround could be to set ADHSC to 0 before entering VLPS and set it back to 1 after the system woke up from VLPS. But I'm wondering why this is not documented somewhere in the datasheet / manual. Is this the expected/normal behavior, or am I doing something wrong?

If I have to swich ADHSC off to save power during VLPS, do I have to add some delay in my code before doing a ADC measurement after I set ADHSC to 1, to give the ADCLK time to switch to the higher frequency?

Best Regards,

Martin

[martinkrause]

Hi Xiangjun Rong,

thank you for your answer!

Best Regards,

Martin

[xiangjun_rong]

Hi, Martin,

Unfortunately, we do not provide the power consumption for each module for Kl03 and the internal circuit of the module.

in order to save power for ADC, I think you should clear the ADHSC bit in ADC_CFG2, and set the ADLPC bit, reduce the ADC clock frequency. After recover from VLPS mode, if you do need high speed sampling,  i do not think the code needs delay after you set the ADHSC bit, setting the ADHSC bit just add two additional ADC clock cycles.

Hope it can help you.

BR

Xiangjun Rong