KEA32 UART1 PIN CONFIGURATION

[raviranjankumar]

Hi,

   I am working on S9KEAZN32AMLH EVB. I want to use UART1 and UART2. But in SIM module there is no option to configure pin for UART1. There is only one register SIM_PINSEL for UART0. As given in reference manual there are three  UART modules and pins are also available then how to configure? 

I am following KEA64 Sub-Family Reference Manual.

Please help.......I am waiting for response. 

Thanks and Regards,

Ravi Ranjan.

[mjbcswitzerland]

Hi Ravi

In the KEA devices you have 3 UARTs.
Their pins are automatically connected when you enable the UART module.

UART0 uses PTB1 for Tx and PTB0 for Rx by default
UART1 uses PTC7 for Tx and PTC6 for Rx (fixed)

UART2 uses PTD7 for Tx and PTD6 for Rx by default

UARTs 0 and 2 have however alternative pin-outs

UART0 Tx on PTA3 and Rx on PTA2

UART2 Tx on PTI1 and Rx on PTI0

In order to choose the alternate pins you use the settings in SIM_PINSEL.

This means that you only need to use the settings in SIM_PINSEL to decide which of the alternatives are to be used (when available) and not to actually connect the UART to its pins.

Regards

Mark

Kinetis: http://www.utasker.com/kinetis.html
KEA:
- http://www.utasker.com/kinetis/TRK-KEA8.html
- http://www.utasker.com/kinetis/TRK-KEA64.html
- http://www.utasker.com/kinetis/TRK-KEA128.html
- http://www.utasker.com/kinetis/FRDM-KEAZN32Q64.html
- http://www.utasker.com/kinetis/FRDM-KEAZ64Q64.html
- http://www.utasker.com/kinetis/FRDM-KEAZ128Q80.html

For optimal code, simulation and support to accelerate your Kinetis developments...

[raviranjankumar]

Hi Mark,

            I have one more doubt. I want to configure UART to 921600 baud rate. I tried with Bus Clock 20000000Hz and 16384000. But I am not able to generate more than 115200. What should I do?

Please Help me.

Thanks and Regard,

Ravi Ranjan.

[mjbcswitzerland]

Ravi

The UARTs are clocked by the Bus clock (max. 20MHz). A divide by 11 (UART_BDH and UART_BDL) gives a Baud rate of 113'636 (closes to 115'200) from 20MHz bus clock.
A maximum Baud rate of 1'249'996 should be possible with the baud rate divider set to 1.
If you don't get the expected rate, check what value has actually been written to the baud gate divide registers.

Regards

Mark

[raviranjankumar]

Hi Mark,

      Thanks for your response. I tried with given formulae in the reference manual. Baud rate = Module clock/(SBR * 16).

and with SDK example code also. more than 115200 is working. but specific 460800 and 921600 not working I checked with 20000000 and 16384000 Bus Clock.  The difference between these baud rates and the baud rate I am getting by changing SBR is more.

I tried with Example code logic also

u16_lSbr = (((u32_lClkSrcFreq)>>4) + (u32_fBaudRate>>1))/u32_fBaudRate;

/* Save off the current value of the UARTx_BDH except for the SBR field */
u8_lTemp = p_stgUartRegsAccess[u8_fUartChSel]->BAUD_HIGH & ~(UART_BDH_SBR_MSK);

p_stgUartRegsAccess[u8_fUartChSel]->BAUD_HIGH = u8_lTemp | UART_BDH_SBR_BIT(u16_lSbr >> 8);
p_stgUartRegsAccess[u8_fUartChSel]->BAUD_LOW = (U8)(u16_lSbr & UART_BDL_SBR_MSK);

Mainly I need 460800 and 921600. Please help.....

Regards,

Ravi Ranjan. 

[mjbcswitzerland]

Ravi

I don't think that these frequencies are possible with this chip.

You need a bus clock of 921600  * 16 = 14.7456MHz (with Baud divider of 1).

Using the FLL and a crystal or external clock requires that the external clock be 31.25kHz..39.06525kHz * [1, 2, 4, 8, 16, 32, 64, 128, 512 or 1024]. The derived input frequency (in the range of 31.25kHz..3906525kHz is then multiplied by 1024 to get the system clock (max. 40MHz) and divided by 1,2,4,8,16,32,64 or 128 to get the bus clock (max. 20MHz)

The bus frequencies possible (to get close to the 14.7456MHz, according to my calculations) are 8MHz..10.000704MHz and 16MHz..20.001408MHz. And so the closest is to use 16MHz bus clock, a Baud divider of 1 to arrive at 1.0MHz Baud. The closest lower frequency is a bus clock of 10.000704MHz with the same Baud divider to get 625.044k Baud.

Using Baud divider of 2 gives possible values of 312.522kBaud and 500kBaud.

Due to the restrictions, the resolution is very limited in this area so I think that if you need the Baud rates that you have shown you will need to use a different chip which allows more flexibility. The FLL capabilities are too limited....

Regards

Mark

[raviranjankumar]

Hi Mark,

   Thank you so much for your support. It was very helpful for me.

Regards,

Ravi Ranjan.

[raviranjankumar]

Hi Mark,

         Thanks for the reply. Now I got it.

Regards,

Ravi