KEA FTM register write enable/disable clarity in WPEN AND WPDIS

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KEA FTM register write enable/disable clarity in WPEN AND WPDIS

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Contributor III

These are two related register descriptions from the KEA Reference Manual.
The description has contradictory information and other parts make it unclear
what is really happening and I hope someone with NXP can clear things up.

I've seen another post here concerning a similar issue with the K64.  The OP didn't get a

straight answer and ended up making a workaround.

In the field descriptions of the FTM0_FMS (Fault Mode Status) register is the following:

Write Protection Enable 

[WPEN]

BIT 6

                     The WPEN bit is the negation of the WPDIS bit.

                     WPEN is set when 1 is written to it.
                     WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS.
                     Writing 0 to WPEN has no effect.
                              0 Write protection is disabled. Write protected bits can be written.
                              1 Write protection is enabled. Write protected bits cannot be written.


In the field descriptions of the FTM0_MODE register is the following:
Write Protection Disable

[WPDIS] 

BIT 2

                     When write protection is enabled (WPDIS = 0), write protected bits cannot be written.
                     When write protection is disabled (WPDIS = 1), write protected bits can be written.
                     The WPDIS bit is the negation of the WPEN bit.
                     WPDIS is cleared when 1 is written to WPEN.
                     WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS.
                              0 Write protection is enabled.

                              1 Write protection is disabled.

The first description from the WPEN field description says, "Writing 0 to WPEN has no effect."
Then just one line down it implies writing to it disables write protection.
It seems clear that reading that bit as zero INDICATES write protection is disabled.

Both of these bit field descriptions have a similar line that don't make it clear what is happening:

"WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS," from the FTM0_FMS register and

"WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS," from the FTM0_MODE register.

Does this mean that if WPEN is 1 WPDIS will also be 1?
Does this mean that if you read WPEN and then you write 1 to WPDIS, WPEN will then be 1?
Who writes to WPDIS? Does it happen automatically?
Does this mean if you write 1 to WPEN it also changes WPDIS to one? In other words they're
linked in hardware to always be opposite to one another?

Can you please clear this up? No pun intended.

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2 Replies

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NXP TechSupport
NXP TechSupport

Hello tomsparks‌,

Does this mean that if WPEN is 1 WPDIS will also be 1?

No, one is the negated part of the other.
Does this mean that if you read WPEN and then you write 1 to WPDIS, WPEN will then be 1?

No, this means that when WPEN is read and WPDIS is set, WPEN will be 0
Who writes to WPDIS? Does it happen automatically?

No, if you want to disable the write protection you need to read WPEN and set WPDIS and WPDIS is cleared when 1 is written to WPEN.
Does this mean if you write 1 to WPEN it also changes WPDIS to one? In other words they're linked in hardware to always be opposite to one another?

They're negated. If you set one of the registers the other will be cleared.

I hope this helps you.

Best Regards,

Alexis Andalon

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Contributor III

Thank you.  Your last sentence answered my question.  If your write to one it will affect the other.

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