KEA ADC overrun misaligns internal FIFO

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KEA ADC overrun misaligns internal FIFO

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phil74
NXP Employee
NXP Employee

Hello,

In order to evaluate the ADC of this MCU I wrote a simple test software to continuously read out one ADC channel (see attachment “main.c”).

I use the FIFO feature of the ADC to always get 8 samples at once per ISR call.

Actually this code works well as long as no overrun occurs in the ADC FIFO (or in other words, as long as I always read the “ADC_R” register before the next ADC sample is available).

But if for some reason I lose at least one ADC sample (FIFO overrun occurs, for example due to a higher priority ISR), the FIFO seems to be out of sync for all future reads. So from this time on, I always get the 8 ADC samples in a wrong order when reading the “ADC_R” register.

The datasheet says that if FIFO is full, then the next conversion will override old data in case of no read action.
This is fine, but it seems then that the internal FIFO pointer has been shifted even for the next interrupts...

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For better understanding, I have attached some pictures of my measurement:

  • “scope_1.png” shows the signals on the MCU pins PTC0 (AD8) and PTE0 (“SCOPE_PIN” in the sample code)
    • Green line: Waveform on the ADC input pin (sawtooth from a waveform generator)
    • Yellow line: Activity of the ADC ISR (low = background task, high = ISR processing).
  • “values_1.png” shows the measured ADC values
    • Gray bars: Count of ADC values fetched in the ISR (array “adc_count_buffer”)
    • Red dots: Measured ADC values (array “adc_buffer” which was filled by reading the FIFO register “ADC_R”)

 

As you can see, I have simulated a FIFO overrun in the middle of the measurement with a short busy wait in the ADC ISR. Before this overrun, all ADC values are correct, but after it the order of the ADC samples is wrong. This makes it impossible to design a robust and reliable firmware, because losing one single ADC sample can lead to permanently wrong ADC results in future.

 

Do you have an idea what’s going wrong here and how I can avoid this?

 

Thanks in advance,

BR,

Philippe

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Ray_V
Contributor V

This definitely looks like a hardware bug.

The oldest conversion gets overwritten by the new conversion, but the front of the FIFO does not get updated.

To avoid this you probably have to set the ADC as the highest priority interrupt.

Alternatively you can try to use the DMA to transfer the FIFO ta a local buffer.

If those are not feasible and you don't mind losing samples you need to check the overrun flag each time the FIFO is going to be read and empty it if the overrun flag is set.

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phil74
NXP Employee
NXP Employee

Code and screen shot

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phil74
NXP Employee
NXP Employee

Hi Ricardo,

It is included in the zip file I have sent you by mail.

Anyway, here is it.

BR,

Philippe

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phil74
NXP Employee
NXP Employee

Hello,

This issue looks like a hardware bug in the FIFO?

Can confirm this?

BR,

Philippe

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ricardoolivare1
NXP Employee
NXP Employee

Hi Phil,

could you please share your main.c file, is not attached in thread. 

thanks!

regards,

Ricardo Olivares 

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phil74
NXP Employee
NXP Employee

Hello,

Any feedback?

BR,

Philippe

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phil74
NXP Employee
NXP Employee

Hello,

Unfortunately the ASCANE bit did not change anything, so the problem still exists.

And detecting an overrun is not possible (unexpected interrupt can arrive anytime), so I don’t know when I have to reset the FIFO...

Do you have any other recommandation ?

BR,

Philippe.

Note : I insert the 2 screeshot that you could not read.scope_1.png

values_1.png

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Can you set the ASCANE bit in ADC_SC4 register and have a try? If you set the bit, the FIFO always use the first dummied FIFO channels when it is enabled.

If the above method can not fix the issue, as a workaround, you can write 0x1F to ADCH bits in ADC_SC1 register to reset the FIFO when overrun event happens.

BTW, I can not see the scope_1.png and values_1.png you submitted.

Hope it can help you.

BR

XiangJun Rong

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