KE04 LVD and POR specification

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KE04 LVD and POR specification

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jun1
Contributor V

Please kindly advise.

Table 4. Questions about LVD and POR specification.(Document Number MKE04P80M48SF0 Data Sheet: Technical Data Rev. 4, 07/2016)


Since LVDRE of PMC_SPMSC1 is 1 by default, I think that low voltage reset is enabled.
PMC_SPMSC2 defaults to 0.
So, does this low voltage reset take place with VLVDL = 0 or VLVW1L?
               Min Typ Max
VLVDL 2.56 2.61 2.66 V
VLVW1L 2.62 2.7 2.78 V
VLVW2L 2.72 2.8 2.88 V
VLVW3L 2.82 2.9 2.98 V
VLVW4L 2.92 3.0 3.08 V

Or does the low-voltage reset not work unless it is written to PMC_SPMSC2.LVDV?

jun

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi jun yamada,

  You are welcome.

   Do you have any further question about this topic?

  If yes, please kindly let me know.

  If your question is solved, please help me to mark the correct answer, just to close this case, thank you!

Have a great day,
Kerry

 

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742 次查看
kerryzhou
NXP TechSupport
NXP TechSupport

Hi jun,

   The reset will be take place with VLVDL:

pastedImage_1.png

The LVWnL is used to give the warning flag, or trigger the interrupt.

Wish it helps you!

If you still have question about it, please kindly let me know.

Have a great day,
Kerry

 

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jun1
Contributor V

thank you for your answer.
It was definitely in the documentation. Thank you for teaching me.

 13.2.4 Low-voltage warning (LVW)

jun

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi jun yamada,

  You are welcome.

   Do you have any further question about this topic?

  If yes, please kindly let me know.

  If your question is solved, please help me to mark the correct answer, just to close this case, thank you!

Have a great day,
Kerry

 

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Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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