Our MKE02Z64VFM4 clock configuration uses the Internal Reference Clock (IRC) in FEI Mode, with the the IRC to 39.0625 kHz and the FLL Multiplier set to 1024, to obtain a nominal maximum clock frequency of 40 MHz. We have not undertaken additional trimming of the Internal Clock Source, and are therefore reliant on the accuracy of the production trimming (+/- 0.5%).
In our application, we have seen repeatable resets of the CPU when the case temperature of the CPU is >= 100C. We have inspected the CPU SIM_SRSI Reset Source Register and confirmed that the source of the reset is the internal Watchdog.
Our reading of section 20.4.5 of the KE02 Family Reference Manual suggests that this behaviour is probably due to our core clock frequency exceeding the maximum allowable value of 40 MHz (noting the IRC Trim accuracy of +/- 0.5%), which is then followed by a Firmware lockup state with a subsequent assertion of the Watchdog and CPU reset – could you please provide a response to the following questions:
Thank you for the assistance - CC
Check my answers bellow,
As you mention this is outside the spec and isn't caracterized but as a test could you try using a lower operation frequency to check if this error also appears?
Until now there isn't any erratas regarding this issue. You could check this document to know which erratas where found.
Thank you for the prompt feedback - that all makes sense.\
The Errata does not currently include any relevant details for our test condition, and we are proceeding with a lower core clock frequency test.
Many thanks for the assistance - CC